Source Core

R

RESET

The Source core remains in the RESET state until the Reset_n signal is deasserted. When in the RESET state, the Source core transmits idle patterns on TDat[15:0] and the Status FIFO is driven to be satisfied (“10”) for all channels.

HUNT

When Reset_n is deasserted, the state machine goes to the HUNT state and sends continuous training patterns on the SPI-4.2 Interface. Once the Source core is enabled (SrcEn=1), the Source Status Interface attempts to acquire synchronization on the FIFO Status Channel. When the Source Status Interface has found the “11” framing pattern, the Source core and monitors for the programmed number of consecutive DIP-2 correct matches (NumDip2Matches). When in the HUNT state, the Status FIFO is driven to be satisfied (“10”) for all channels.

SYNC

If the number of correct DIP-2 matches are received (NumDip2Matches), the Source core goes into the SYNC state. In this state, the core transmits the flow control data received on the status path (TStat[1:0]) onto the user interface. It also transmits the data that has been written into the FIFO on the SPI-4.2 Lite data bus (TDat[15:0]). If an incorrect framing pattern (of four consecutive "11") is received, a set number of consecutive DIP-2 errors (defined by NumDip2Errors) are received, or if SrcEn is deasserted, the state machine returns to the HUNT State.

Reset Asserted

RESET

The Source core remains in the reset state until the following condition is true: Reset_n is deasserted

The source core transmits idle patterns on TDat[15:0] while in the reset state.

Reset Asserted

HUNT

The Source core remains in the hunt state until the following conditions are:

--The PHY device is no longer sending framing (TSTAT /= "11")

--Once framing is not being received, a consecutive number of DIP2 matches (defined by the parameter <NumDip2Matches> is received.

--Source is enabled

Each "11" to non "11" transition is translated as a start of a status sequence.

The source core transmits training patterns on TDat[15:0] while in the hunt state.

<NumDip2Errors> Consecutive Incorrect DIP-2 Calculations Deleted or Source Disabled

SYNC

In the sync state, the Source core has completed the start-up sequence and normal core operation is enabled.

In normal operation, the Source core transmits data bursts that have been written into the Source FIFO. It also sends periodic training patterns on TDat and continuously checks DIP-2 parity on TStat.

Figure 4-37:Source Startup Sequence State Machine

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual Reset
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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