Xilinx UG181 manual Timespecs for Clocks, Source Core Required Constraints

Source Core Required Constraints

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•NET "TSClk_P" TNM_NET = "TSClk" (for source status I/O type of LVDS);

The following constraints are for the Source core user interface clocks, and are only required if the user interface signals are not looped back to the source core user interface.

•NET "SrcCalClk" TNM_NET = "SrcCalClk";

•NET "SrcFFClk" TNM_NET = "SrcFFClk";

•NET "SrcStatClk" TNM_NET = "SrcStatClk";

Timespecs for Clocks

The following constraints are for the Source core clocks, and are always required. Note the generated SPI-4.2 Lite core may have different timing constraints than the examples provided below.

•TIMESPEC "TS_SysClk_P" = PERIOD "SysClk_P" 170MHz HIGH 50% INPUT_JITTER 200ps;

•TIMESPEC "TS_TSClk" = PERIOD "TSClk" 43MHz HIGH 50%;

The following constraints are for the Source core user interface clocks, and are only required when the respective clocks are used.

•TIMESPEC "TS_SrcCalClk" = PERIOD "SrcCalClk" 43MHz HIGH 50%;

•TIMESPEC "TS_SrcFFClk" = PERIOD "SrcFFClk" 170MHz HIGH 50% I NPUT_JITTER 300 ps;

•TIMESPEC "TS_SrcStatClk" = PERIOD "SrcStatClk" 43MHz HIGH 50%;

These constraints specify the frequency and duty cycle of the clock signal. For the high frequency clocks, clock jitter is also specified. You can modify these values based on target performance.

Maxdelay for Reset

The following constraints are for the Source core reset signals, and are always required. Note the generated SPI-4.2 Lite core may have different timing constraints than the examples provided below.

•NET "<src_instance_name>/U0/pl4_lite_src_reset0/src_tsclk_reset/ reset_out_i" MAXDELAY = 5.8 ns;

•NET "<src_instance_name>/U0/pl4_lite_src_reset0/src_ff_clk_reset_/ reset_out_i" MAXDELAY = 5.8 ns;

•NET "<src_instance_name>/U0/pl4_lite_src_reset0/src_ff_clk_rst/ fifo_reset_out_i" MAXDELAY = 5.8 ns;

•NET "<src_instance_name>/U0/pl4_lite_src_reset0/src_clk_rst/ reset_out_i" MAXDELAY = 5.8 ns;

•NET "<src_instance_name>/U0/pl4_lite_src_reset0/src_clk_rst/ fifo_reset_out_i" MAXDELAY = 5.8 ns;

The MAXDELAY values differ based on target speed grade and core performance.

Placement Constraints

Although the SPI-4.2 Lite core does not require fixed pinouts, there are several placement constraints that are critical for meeting performance requirements and for processing

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 105

UG181 June 27, 2008