Sink Almost Full Threshold Negate

Chapter 2: Core Architecture

Table 2-6:Sink Static Configuration Signals (Continued)

Name	Direction	Range	Description

SnkAFThresNegate[8:0]	Static	SnkAFThresAssert to	Sink Almost Full Threshold Negate: The
	Input	508	SnkAFThresNegate parameter defines the minimum
		Values less than	number of empty FIFO locations that exist when
		SnkAFThresAssert are	SnkAlmostFull_n is deasserted. Note that the negate
		set to	threshold must be greater or equal to the assert
		SnkAFThresAsset.	threshold (SnkAFThresAssert).
		Values greater than	When SnkAlmostFull_n is deasserted, the core stops
		508 are set to 508.	When SnkAlmostFull_n is deasserted, the core stops
		508 are set to 508.	sending flow control (deasserts SnkAlmostFull_n) and
			sending flow control (deasserts SnkAlmostFull_n) and
			resumes transmission of valid FIFO status levels. This
			indicates to the transmitting device that additional
			data can be sent.

RSClkDiv	Static	n/a	Sink Status Clock Divide: This static input is used to
	Input		determine if the RSClk is 1/4 of the data rate, which is
			compliant with the OIF specification, or 1/8 of the data
			rate, which is required by some PHY ASSPs:
			0: RSClkDiv = 1/4 rate (default value)
			1: RSClkDiv = 1/8 rate

RSClkPhase	Static	n/a	Sink Status Clock Phase: This static input determines
	Input		whether the FIFO Status Channel data (RStat[1:0])
			changes on the rising edge of RSClk or the falling edge
			of RSClk:
			0: RSClkPhase = rising edge of RSClk (default value)
			1: RSClkPhase = falling edge of RSClk

FifoAFMode[1:0]	Static	n/a	Sink Almost Full Mode: Selects the mode of operation
	Input		for the Sink interface when the Sink core reaches the
			Almost Full threshold (SnkAFThresAssert).
			If FifoAFMode is set to “00,” the Sink interface goes
			out-of-frame when the core is almost full, and the Sink
			Status logic sends the framing sequence “11” until Sink
			core is not almost full.
			If FifoAFMode is set to “01,” the Sink interface remains
			in frame (SnkOof deasserted), and the Sink Status logic
			sends satisfied “10” on all channels until
			SnkAlmostFull_n is deasserted.
			If FifoAFMode is set to “10” or “11,” the Sink interface
			will remain in frame (SnkOof deasserted), and the Sink
			Status logic continues to drive out the user’s status
			information (i.e., continues in normal operation). In
			this case, you should take immediate action to prevent
			overflow and loss of data.

28	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Sink Almost Full Threshold Negate

Models: UG181

Sink Almost Full Threshold Negate: The

SPI-4.2 Lite v4.3 User Guide

UG181 specifications