R

Appendix C: SPI-4.2 Lite Core Verification

SPI-4.2 bus traffic that caused the SPI-4.2 Lite sink FIFO to be constantly almost full

Backend data traffic that caused the SPI-4.2 Lite source FIFO to be constantly almost full

SPI-4.2 bus traffic that caused the sink FIFO to overflow

Backend data traffic that caused the source FIFO to overflow

Verification of invalid data

SPI-4.2 bus traffic that contained incorrect DIP-4 values

SPI-4.2 status traffic that contained incorrect DIP-2 values

SPI-4.2 status traffic that indicated that the receiving end of the SPI-4.2 Lite source block was out of frame

SPI-4.2 bus traffic that violated SOP spacing and had incorrect control word formats

SPI-4.2 bus traffic that contained data bursts that were not preceded by payload control words

SPI-4.2 bus traffic that terminated on non-credit boundaries with no EOP.

SPI-4.2 bus traffic that contained reserved control words

Backend data traffic that contained no EOP with non-zero MODs.

The behavior of the core was fully verified for a range of core configurations. It was also fully verified for the following range of clock frequencies.

SPI-4.2 bus clock: 100 MHz to 275 MHz

SrcFFClk and SnkFFClk: 50 MHz to 275 MHz

SnkStatClk and SrcStatClk: 20 MHz to 100 MHz

SrcCalClk and SnkCalClk: 20 MHz to 100 MHz

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

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Xilinx UG181 manual Appendix C SPI-4.2 Lite Core Verification

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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