R
Chapter 2
Core Architecture
This chapter describes the
System Overview
The
•Sink Core. Receives data from the
•Source Core. Transmits data on the
Figure 2-1 illustrates the interfaces of the SPI-4.2 Lite core and shows it in a typical link- layer application.
In the link layer example, the SPI-4.2 interface connects an external physical-layer device to
alink-layer implemented in a Virtex™-4 FPGA. The user logic reads data from the Sink core and writes data into the Source core. A standard FIFO interface is provided for this
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UG181 June 27, 2008