Xilinx UG181 manual Source Core Interfaces, RDClk0USER This clock

R

Chapter 2: Core Architecture

Table 2-9:Sink Core Clocks: User Clocking

Clock Pins	Direction	Description	Max. Frequency
RDClk0_USER	Input	RDClk0_USER: This clock	Virtex-5: 275 MHz
	(User Interface)	is used for clocking the	Virtex-4: 190 MHz
		internal logic of the core.
			Virtex-II Pro: 160 MHz
			Virtex-II: 160 MHz
			Spartan-3: 115 MHz
			Spartan-3E: 90 MHz
			Spartan-3A/3AN/3A DSP:
			105 MHz
RDClk180_USE	Input	RDClk180_USER: This	Virtex-5: 275 MHz
R	(User Interface)	clock is the inverted	Virtex-4: 190 MHz
		equivalent of
			Virtex-II Pro: 160 MHz
		RDClk0_USER. It is used
			Virtex-II: 160 MHz
		for clocking the internal
		logic of the core.	Spartan-3: 115 MHz
			Spartan-3E: 90 MHz
			Spartan-3A/3AN/3A DSP:
			105 MHz

Source Core Interfaces

The Source core includes five functional modules:

•Source Data FIFO

•Source Data Transmit

•Source Status Registers

•Source Calendar

•Source Status Receive

The Source core is comprised of the following interfaces:

•Source SPI-4.2 Interface

•Source User Interface

♦Source Control and Status Interface

♦Source FIFO Interface

♦Source Status and Flow Control Interface

-Calendar Control Interface

-Status FIFO Interface

♦Source Configuration Signals Interface

♦Source Clocking Interface

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		UG181 June 27, 2008