R

Chapter 4: Designing with the Core

channel 2 and an SOP for channel 1, followed by three 16-bit words. The last control word (C4) is an EOP for channel 1.

The data received on the SPI-4.2 Interface is processed and stored in the Sink FIFO. Figure 4-1also shows the data being read out of the FIFO and uses forward slashes to indicate that there is latency in processing and storing the SPI-4.2 data. The first 64-bit word on the FIFO interface contains the two 16-bit words received for channel 1 with an EOP. The second 64-bit word contains the two words received for channel 2 with an EOP. The last 64-bit word on the FIFO interface contains the three words written for channel 1. When the last word is read out of the FIFO, both the SnkFFSOP and SnkFFEOP for channel 1 are asserted.

RDClk_P

RDat_P

C1 1A 1B C2 2A 2B C3 1A 1B 1C C4

 

 

RCtl_P

 

 

 

SnkFFClk

 

 

 

SnkFFRdEn_n

 

 

 

SnkFFAddr

CH1

CH2

CH1

SnkFFData

1A 1B -- --

2A 2B -- --

1A 1B 1C --

SnkFFMod

100

100

110

SnkFFSOP

 

 

 

SnkFFEOP

 

 

 

SnkFFValid

 

 

 

Figure 4-1:SPI-4.2 Interface to the 64-Bit User Interface

Sink Data Path: Example 2

The Sink core automatically and optimally handles any size packet including short packets (less than eight cycles apart), which have multiple SOPs or payload control words.

There are two scenarios in which short packets can be received:

•Received SOPs that are less than eight cycles apart. Data is passed through the core as received and a SnkBusErr is flagged, indicating a protocol violation.

•Received Payload Control words that are less than eight cycles apart. Though the SPI-4.2 specification requires that successive SOPs must occur not less than eight cycles apart, there is no restriction on payload control words, which are not SOPs. The Sink core can process single payload control words followed by single data words (CTL-DATA-CTL-DATA-CTL, etc.). Because this is not a protocol violation, no SnkBusErr is asserted.

Figure 4-2shows the transfer of short packets from the SPI-4.2 Interface through the Sink FIFO to the 64-bit user interface. Because each packet contains fewer than 14 bytes, or seven clock cycles of data, idle control word insertion is necessary to meet the start-of- packet spacing requirement of eight cycles. The transfer on the SPI-4.2 Interface begins with a payload control word (C1), indicating a start of packet (SOP) on channel 1. Next, two clock cycles, of two bytes each, are used to transfer the data associated with channel 1. The transfer concludes with an end-of-packet control word (C2). The transfer being fewer

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

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Xilinx UG181 manual 1SPI-4.2 Interface to the 64-Bit User Interface
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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