Sink Core

R

than 14 bytes, four idle cycles are required to meet the SOP spacing requirement. After the four idle cycles, the transfer begins with a start-of-packet control word (C3) for channel 2. Next, three clock cycles (of two bytes each) are used to transfer the data associated with channel 2. The transfer concludes with an end-of-packet control word (C4).

Figure 4-2also shows the data being read out of the FIFO and indicates with forward slashes that there is latency in processing and storing the SPI-4.2 data. The first 64-bit word on the FIFO interface contains the four bytes of valid data received for channel 1. The control signals SnkFFSOP and SnkFFEOP are active, indicating that this is the start and end of the packet for channel 1. The second 64-bit word contains the six bytes of valid data for channel 2, and the control signals SnkFFSOP and SnkFFEOP are both asserted.

RDClk_P

RDat_P

C1 1A 1B C2 I I I I C3 2A 2B 2C C4 I I

 

RCtl_P

 

 

SnkFFClk

 

 

SnkFFRdEn_n

 

 

SnkFFAddr

CH1

CH2

SnkFFData

1A 1B -- --

2A 2B 2C --

SnkFFMod

100

110

SnkFFSOP

 

 

SnkFFEOP

 

 

Figure 4-2:Sink Data Path - Short Packet Transfers with Minimum SOP Spacing Enforced

Table 4-1provides example formatting for the data and control received on the SPI-4.2 Interface. This data is formatted and presented on the 64-bit Sink FIFO Interface. Control words are shown in binary and payload transfers are shown as hexadecimal. After an SOP is received, the following 16-bit word transfer is left justified when written into the FIFO (written to the most significant 16 bits). For the 64-bit interface, the 16 bits will be in the SnkFFData[63:48]. The table shows the receipt of an SOP for channel 2, then a series of payload word transfers. The DIP-4 parity depends on this control word and any proceeding transfer, and it is shown in the table as “pppp.”

Following this example, two additional tables show the mapping between SPI-4.2 Control Words and packet status signals for a 64-bit user interface (Table 4-2) and for a 32-bit user interface (Table 4-3).

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual SnkFFSOP SnkFFEOP
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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