Multiple Core Implementations

R

);

When instantiating the cores, there are several synthesis attributes that must be included. The cores need to be defined as black boxes for the synthesis tool, and automatic insertion of IBUF or OBUF signals for the SPI-4.2 Lite interface signals must be disabled.

For example, in VHDL and Synplicity:

Attribute syn_black_box: boolean ;

Attribute black_box_pad_pin: string ;

Attribute syn_black_box of pl4_lite_snk_top1 : component is true;

Attribute black_box_pad_pin of pl4_lite_snk_top1: component is “RDClk_P, RDClk_N, RDat_P(15:0), RDat_N(15:0), RCtl_P, RCtl_N” ;

Attribute syn_black_box of pl4_lite_snk_top2 : component is true;

Attribute black_box_pad_pin of pl4_lite_snk_top2 : component is “RDClk_P, RDClk_N, RDat_P(15:0), RDat_N(15:0), RCtl_P, RCtl_N”;

Attribute syn_black_box of pl4_lite_src_top1 : component is true ;

Attribute black_box_pad_pin of pl4_lite_src_top1: component is “SysClk_P, SysClk_N, TDClk_P, TDClk_N, TDat_P(15:0), TDat_N(15), TCtl_P, TCtl_N” ;

Attribute syn_black_box of pl4_lite_src_top2 : component is true ;

Attribute black_blox_pad_pin of pl4_lite_src_top2 : component is “SysClk_P, SysClk_N, TDClk_P, TDClk_N, TDat_P(15:0), TDat_N(15:0), TCtl_P, TCtl_N” ;

Examples of the attributes are available in the delivered example wrapper files:

<proj>/implement/<vhdl/verilog>/*.v<vhd>

Generating the Cores

For each core that will be instantiated, unique netlists (with unique component names) must be generated using the Xilinx CORE Generator. Each NGC file must also be renamed to match the component names in the top-level file.

For example:

pl4_lite_snk_top1.ngc

pl4_lite_snk_top2.ngc

pl4_lite_src_top1.ngc

pl4_lite_src_top2.ngc

Creating Top-Level UCF File

When instantiating multiple cores, each core is generated separately by the CORE Generator system and includes a separate top-level UCF file. The user must merge the top- level UCF files generated for each core to produce a single UCF file with all required constraints.

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual Generating the Cores, Creating Top-Level UCF File, Multiple Core Implementations

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.