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Xilinx UG181 Generating the Cores, Creating Top-Level UCF File, Multiple Core Implementations

Models: UG181

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Multiple Core Implementations

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When instantiating the cores, there are several synthesis attributes that must be included. The cores need to be defined as black boxes for the synthesis tool, and automatic insertion of IBUF or OBUF signals for the SPI-4.2 Lite interface signals must be disabled.

For example, in VHDL and Synplicity:

Attribute syn_black_box: boolean ;

Attribute black_box_pad_pin: string ;

Attribute syn_black_box of pl4_lite_snk_top1 : component is true;

Attribute black_box_pad_pin of pl4_lite_snk_top1: component is “RDClk_P, RDClk_N, RDat_P(15:0), RDat_N(15:0), RCtl_P, RCtl_N” ;

Attribute syn_black_box of pl4_lite_snk_top2 : component is true;

Attribute black_box_pad_pin of pl4_lite_snk_top2 : component is “RDClk_P, RDClk_N, RDat_P(15:0), RDat_N(15:0), RCtl_P, RCtl_N”;

Attribute syn_black_box of pl4_lite_src_top1 : component is true ;

Attribute black_box_pad_pin of pl4_lite_src_top1: component is “SysClk_P, SysClk_N, TDClk_P, TDClk_N, TDat_P(15:0), TDat_N(15), TCtl_P, TCtl_N” ;

Attribute syn_black_box of pl4_lite_src_top2 : component is true ;

Attribute black_blox_pad_pin of pl4_lite_src_top2 : component is “SysClk_P, SysClk_N, TDClk_P, TDClk_N, TDat_P(15:0), TDat_N(15:0), TCtl_P, TCtl_N” ;

Examples of the attributes are available in the delivered example wrapper files:

<proj>/implement/<vhdl/verilog>/*.v<vhd>

Generating the Cores

For each core that will be instantiated, unique netlists (with unique component names) must be generated using the Xilinx CORE Generator. Each NGC file must also be renamed to match the component names in the top-level file.

For example:

pl4_lite_snk_top1.ngc

pl4_lite_snk_top2.ngc

pl4_lite_src_top1.ngc

pl4_lite_src_top2.ngc

Creating Top-Level UCF File

When instantiating multiple cores, each core is generated separately by the CORE Generator system and includes a separate top-level UCF file. The user must merge the top- level UCF files generated for each core to produce a single UCF file with all required constraints.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

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UG181 June 27, 2008

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Xilinx UG181 manual Generating the Cores, Creating Top-Level UCF File, Multiple Core Implementations

Contents

UG181 June 27 LogiCORE IP SPI-4.2 LiteDate Version Revision SPI-4.2 Lite v4.3 User Guide UG181 June 27Table of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide 1SPI-4.2 Lite Core in a Typical Link Layer Application Schedule of Figures30Addressable Status Fifo Interface 4-Channel Configuration Generating the Core Designing with the Core Schedule of TablesAppendix a SPI-4.2 Lite Control Word About This Guide ContentsTypographical ConventionsConventions Online DocumentPreface About This Guide About the Core IntroductionRecommended Design Experience Additional Core ResourcesFeedback Technical SupportSPI-4.2 Lite Core DocumentSystem Overview Core ArchitectureSource Core Sink CoreCore Architecture Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram RCtlN Sink SPI-4.2 InterfaceSink Control and Status Interface Sink User InterfaceSink Fifo Interface 3Sink Fifo Signals NameCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate RDClk0 General Purpose Sink Clocking InterfaceRDClk0USER This clock Source Core InterfacesSource Core Interfaces Source SPI-4.2 InterfaceDomain Source User InterfaceSource Control and Status Interface 16 bytes with no EOP Name Direction Clock Description Domain Source Fifo Interface14 Source Status Fifo Signals Source Status Address Source Static Configuration InterfaceSource Almost Full Threshold Assert Source Calendar Period The SrcCalendarM Source Clocking InterfaceSysClk0 General Purpose Domain Core Architecture Core Generator Graphical User Interface Generating the CoreSink Status Options Screen Main ScreenComponent Name Core OptionsFlow Control CalendarStatus Interface Synchronization Sink Other Options ScreenFifo Threshold Source Status Options Screen Clock ModeClocking Clock DistributionBursting Source Other Options ScreenBurst Size in Credits Burst ModeSysClk Distribution TSClk DistributionCalendar COE File Format Designing with the Core Understand Signal PipeliningGeneral Design Guidelines Know the Degree of DifficultyInitializing the SPI-4.2 Lite Core Recognize Timing Critical SignalsKeep it Registered Use Supported Design FlowsBasic Operation Sink CoreSPI-4.2 Interface Sink Data Path Example1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP Sink Fifo RCtlSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Almost Empty Sink Fifo Interface SignalsSink Almost Full Sink Fifo EmptySink Overflow Sink Status and Flow Control SignalsInitializing the Calendar In-Circuit Sink Calendar Initialization7Sink Calendar Initialization Sink Flow Control8Typical Flow Control Implementation for 4-Channel System 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3 Sink Status Fifo Interface ExampleSink Status Fifo Status Interface Example Insertion of DIP2 Errors Sink Static Configuration SignalsFifo Almost Full Mode FifoAFMode and Sink Almost Full12FIFO Almost Full Mode Sink Data Capture Implementation Fifo Almost Full Mode 10 orStatic Alignment DCM Alignment Implementation ConsiderationsSynchronization and Start-up Hunt ResetSync Wait Sync Data Error HandlingSync Train In-Frame and Out-of-Frame BehaviorSink SPI-4.2 Bus Error and Sink Bus Error Status70 Sink Fifo Burst ErrorEOP Abort Handling Loss of RDClkSequential Payload Control Words Sink DIP-4 Error HandlingSequential End-of-Burst Control Words 18Example of Error Flag SnkFFDIP4Err Reserved Control Words Source CoreSource Core Source Data Path Example22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Source Control and Status Signals Inserting DIP4 ErrorsTransmitting Idle Cycles Source Fifo Almost Full Source Fifo Interface Signals24Source Fifo Almost-full Condition Source Fifo OverflowInsertion of DIP-4 Errors Source Status and Flow Control SignalsWriting to the Source Fifo 27Typical User Design Example Source Calendar Initialization28Source Calendar Initialization Source Flow Control Addressable Status Interface29Addressable Status Fifo Interface Addressable Status Fifo Interface Example30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Burst Mode Source Static Configuration Signals35Example Of Source Burst Mode = Source Burst Mode ExampleReset Source Behavior After Synchronization Source Behavior Before SynchronizationEOP Abort Insertion Source Out of FrameSource Pattern Error Handling Source DIP-2 Error HandlingSource Status Frame Word Handling Incorrect Burst TerminationDesigning with the Core Overview Constraining the CoreSink Core Required Constraints Timing ConstraintsTime Names for Clocks Maxdelay for ResetTimespecs for Clocks Constraining the CoreClock Delay in Iserdes Phase Shift for DCMDCM and Static Alignment Constraints Sink Core Required ConstraintsPlacement Placement ConstraintsSink Core Optional Constraints IDelayCtrlStandards Constraints IOB Register PackingArea Group Constraints Source Core Required ConstraintsTiming Ignore Constraints Timenames for ClocksSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsConstraints Migration User ConstraintsNew Target Region or Device Package Target Device Modifying the UCF FileSink Core Source CoreInst TSClk LOC = Bank3 Sink Clocking Options Special Design ConsiderationsEmbedded Clocking Special Design Considerations User ClockingSink Clocking Options Global Clocking2Sink Core User Clocking Resources Clocking Option 3Sink User Clocking Global Clocking Regional ClockingSource Clocking Options Source Clocking Options5Source Clocking Master and Slave Implementation Master ClockingIOB 8Source Clocking Regional Clocking for SysClk 3SysClk Clocking Resources Clocking Option Slave ClockingTSClk Clocking Resources Clocking Option Instantiating Multiple Cores Multiple Core ImplementationsCreating Top-Level UCF File Generating the CoresMultiple Core Implementations Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Functional Simulation Simulating and Implementing the CoreGenerating a Simulation Model Generating a Simulation Model with Initialized CalendarSimulating and Implementing the Core Timing SimulationSynthesis of Example Design SynthesisSynplify SynthesisExample Design Script Xilinx Tool FlowNGDBuild Mapping the DesignGenerating a Bitstream Static Timing AnalysisXilinx Tool Flow 130 Eops SPI-4.2 Lite Control WordDIP-4 Example SPI-4.2 Lite Calendar ProgrammingAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification