Manuals / Xilinx / Power Tools / Welder

Xilinx UG181 manual Clocking Considerations

Models: UG181

1 136

Download 136 pages 34.17 Kb

Page 122

R

Chapter 6: Special Design Considerations

For each core constraints, the instance name in the UCF file must be modified to match the instance names in the top-level RTL design. For the timing and I/O pin location constraints, change the names to match the I/O ports declared in the top-level design as shown in the examples below.

•TNMs and TIMESPECs:

Net “First_RDClk_P” TNM_NET = “First_RDClk_P”;

TIMESPEC “TS_First_RDClk_P” = PERIOD “First_RDClk_P” 100 MHz HIGH 50%;

•I/O pins location:

INST “First_RDat*” LOC = BANK5”; INST “First_RCtl” LOC = “BANK5”;

INST “First_RDClk” LOC = “BANK3 “;

INST “First_TDat*” LOC = “BANK9”;

INST “First_TCtl” LOC = “BANK9”;

See Chapter 5, “Constraining the Core” for details on how to place the Area Group, and IO Bank components.

Clocking Considerations

If the reference clock (SysClk) can be shared among different Source cores, we recommend that Source cores with slave clocking be used in the design with the external clocking module (pl4_lite_src_clk.v/vhd). For Virtex-4 or Virtex-5 FPGA designs, the SPI-

4.2Source Status FIFO Clocks (TSClk) can be implemented using regional clock buffer resources to further reduce the number of global clocks and DCMs used in the design.

The user can also use a single Source core in and use the clock outputs (SysClk180_GP other Source cores in slave clocking mode.

For example:

master clocking mode with global clock option and SysClk0_GP) of this core to drive the

first_pl4_lite_src_top0 : pl4_lite_src_top1 --- Master clocking mode

port map (

.........

SysClk180_GP => SysClk180_GP ;

SysClk0_GP => SysClk0_GP;

...........

);

second_pl4_lite_src_top0 : pl4_lite_src_top2 --- Slave clocking mode

port map (

............

SysClkDiv_GBSLV => SysClk180_GP;

SysClk0_GBSLV => SysClk0_GP;

122	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

Image 122

Xilinx UG181 manual Clocking Considerations

Contents

LogiCORE IP SPI-4.2 Lite UG181 June 27SPI-4.2 Lite v4.3 User Guide UG181 June 27 Date Version RevisionTable of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide Schedule of Figures 1SPI-4.2 Lite Core in a Typical Link Layer Application30Addressable Status Fifo Interface 4-Channel Configuration Schedule of Tables Generating the Core Designing with the CoreAppendix a SPI-4.2 Lite Control Word Contents About This GuideConventions TypographicalOnline Document ConventionsPreface About This Guide Recommended Design Experience IntroductionAbout the Core Additional Core ResourcesSPI-4.2 Lite Core Technical SupportFeedback DocumentCore Architecture System OverviewCore Architecture Sink CoreSource Core Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram Sink SPI-4.2 Interface RCtlNSink User Interface Sink Control and Status Interface3Sink Fifo Signals Name Sink Fifo InterfaceCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate Sink Clocking Interface RDClk0 General PurposeSource Core Interfaces RDClk0USER This clockSource SPI-4.2 Interface Source Core InterfacesSource User Interface DomainSource Control and Status Interface 16 bytes with no EOP Source Fifo Interface Name Direction Clock Description Domain14 Source Status Fifo Signals Source Static Configuration Interface Source Status AddressSource Almost Full Threshold Assert Source Clocking Interface Source Calendar Period The SrcCalendarMSysClk0 General Purpose Domain Core Architecture Generating the Core Core Generator Graphical User InterfaceComponent Name Main ScreenSink Status Options Screen Core OptionsStatus Interface CalendarFlow Control Fifo Threshold Sink Other Options ScreenSynchronization Clocking Clock ModeSource Status Options Screen Clock DistributionSource Other Options Screen BurstingSysClk Distribution Burst ModeBurst Size in Credits TSClk DistributionCalendar COE File Format General Design Guidelines Understand Signal PipeliningDesigning with the Core Know the Degree of DifficultyKeep it Registered Recognize Timing Critical SignalsInitializing the SPI-4.2 Lite Core Use Supported Design FlowsSPI-4.2 Interface Sink CoreBasic Operation Sink Data Path Example1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP RCtl Sink FifoSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Interface Signals Sink Fifo Almost EmptySink Fifo Empty Sink Almost FullSink Status and Flow Control Signals Sink OverflowSink Calendar Initialization Initializing the Calendar In-CircuitSink Flow Control 7Sink Calendar Initialization8Typical Flow Control Implementation for 4-Channel System Sink Status Fifo Interface Example 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3Sink Status Fifo Status Interface Example Fifo Almost Full Mode Sink Static Configuration SignalsInsertion of DIP2 Errors FifoAFMode and Sink Almost Full12FIFO Almost Full Mode Static Alignment Fifo Almost Full Mode 10 orSink Data Capture Implementation DCM Alignment Implementation ConsiderationsSynchronization and Start-up Sync Wait ResetHunt Sync Train Error HandlingSync Data In-Frame and Out-of-Frame BehaviorEOP Abort Handling Sink Fifo Burst ErrorSink SPI-4.2 Bus Error and Sink Bus Error Status70 Loss of RDClkSequential End-of-Burst Control Words Sink DIP-4 Error HandlingSequential Payload Control Words 18Example of Error Flag SnkFFDIP4Err Source Core Reserved Control WordsSource Data Path Example Source Core22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Transmitting Idle Cycles Inserting DIP4 ErrorsSource Control and Status Signals Source Fifo Interface Signals Source Fifo Almost FullSource Fifo Overflow 24Source Fifo Almost-full ConditionWriting to the Source Fifo Source Status and Flow Control SignalsInsertion of DIP-4 Errors Source Calendar Initialization 27Typical User Design ExampleSource Flow Control Addressable Status Interface 28Source Calendar InitializationAddressable Status Fifo Interface Example 29Addressable Status Fifo Interface30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Static Configuration Signals Source Burst ModeSource Burst Mode Example 35Example Of Source Burst Mode =Reset EOP Abort Insertion Source Behavior Before SynchronizationSource Behavior After Synchronization Source Out of FrameSource Status Frame Word Handling Source DIP-2 Error HandlingSource Pattern Error Handling Incorrect Burst TerminationDesigning with the Core Sink Core Required Constraints Constraining the CoreOverview Timing ConstraintsTimespecs for Clocks Maxdelay for ResetTime Names for Clocks Constraining the CoreDCM and Static Alignment Constraints Phase Shift for DCMClock Delay in Iserdes Sink Core Required ConstraintsPlacement Constraints PlacementStandards Constraints IDelayCtrlSink Core Optional Constraints IOB Register PackingTiming Ignore Constraints Source Core Required ConstraintsArea Group Constraints Timenames for ClocksSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsNew Target Region or Device Package User ConstraintsConstraints Migration Sink Core Modifying the UCF FileTarget Device Source CoreInst TSClk LOC = Bank3 Embedded Clocking Special Design ConsiderationsSink Clocking Options User Clocking Special Design Considerations2Sink Core User Clocking Resources Clocking Option Global ClockingSink Clocking Options Regional Clocking 3Sink User Clocking Global ClockingSource Clocking Options Source Clocking OptionsMaster Clocking 5Source Clocking Master and Slave ImplementationIOB 8Source Clocking Regional Clocking for SysClk TSClk Clocking Resources Clocking Option Slave Clocking3SysClk Clocking Resources Clocking Option Multiple Core Implementations Instantiating Multiple CoresMultiple Core Implementations Generating the CoresCreating Top-Level UCF File Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Generating a Simulation Model Simulating and Implementing the CoreFunctional Simulation Generating a Simulation Model with Initialized CalendarTiming Simulation Simulating and Implementing the CoreSynplify SynthesisSynthesis of Example Design SynthesisNGDBuild Xilinx Tool FlowExample Design Script Mapping the DesignXilinx Tool Flow Static Timing AnalysisGenerating a Bitstream 130 SPI-4.2 Lite Control Word EopsDIP-4 SPI-4.2 Lite Calendar Programming ExampleAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification