R

Chapter 6: Special Design Considerations

For each core constraints, the instance name in the UCF file must be modified to match the instance names in the top-level RTL design. For the timing and I/O pin location constraints, change the names to match the I/O ports declared in the top-level design as shown in the examples below.

TNMs and TIMESPECs:

Net “First_RDClk_P” TNM_NET = “First_RDClk_P”;

TIMESPEC “TS_First_RDClk_P” = PERIOD “First_RDClk_P” 100 MHz HIGH 50%;

I/O pins location:

INST “First_RDat*” LOC = BANK5”; INST “First_RCtl” LOC = “BANK5”;

INST “First_RDClk” LOC = “BANK3 “;

INST “First_TDat*” LOC = “BANK9”;

INST “First_TCtl” LOC = “BANK9”;

See Chapter 5, “Constraining the Core” for details on how to place the Area Group, and IO Bank components.

Clocking Considerations

If the reference clock (SysClk) can be shared among different Source cores, we recommend that Source cores with slave clocking be used in the design with the external clocking module (pl4_lite_src_clk.v/vhd). For Virtex-4 or Virtex-5 FPGA designs, the SPI-

4.2Source Status FIFO Clocks (TSClk) can be implemented using regional clock buffer resources to further reduce the number of global clocks and DCMs used in the design.

The user can also use a single Source core in and use the clock outputs (SysClk180_GP other Source cores in slave clocking mode.

For example:

master clocking mode with global clock option and SysClk0_GP) of this core to drive the

first_pl4_lite_src_top0 : pl4_lite_src_top1 --- Master clocking mode

port map (

.........

SysClk180_GP => SysClk180_GP ;

SysClk0_GP => SysClk0_GP;

...........

);

second_pl4_lite_src_top0 : pl4_lite_src_top2 --- Slave clocking mode

port map (

............

SysClkDiv_GBSLV => SysClk180_GP;

SysClk0_GBSLV => SysClk0_GP;

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UG181 June 27, 2008

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Xilinx UG181 manual Clocking Considerations

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.