Bytes with no EOP | Xilinx UG181 guide

Chapter 2: Core Architecture

Table 2-11:Source Control and Status Signals (Continued)

Name	Direction	Clock	Description
Name	Direction	Domain	Description
		Domain

SrcPatternErr	Output	SrcFFClk	Source Data Pattern Error: When this signal is asserted (active high), it
			indicates that the data pattern written into the Source FIFO is illegal. Illegal
			patterns include the following:
			• Burst of data terminating on a non-credit boundary (not a multiple
			of 16 bytes) with no EOP
			• Non-zero value on SrcFFMod when SrcFFEOP is deasserted
			This signal is asserted for one clock cycle each time an illegal data pattern is
			written into the Source FIFO.

IdleRequest	Input	SrcFFClk	Idle Request: This is an active high signal that requests idle control words be
			sent out of the Source SPI-4.2 interface. The Source core responds by sending
			out idle control words at the next burst boundary. This signal overrides normal
			SPI-4.2 data transfer requests, but it does not override training sequence
			requests (TrainingRequest).
			Activating the request for idle cycles does not affect the Source FIFO contents
			or the user side operation.

TrainingRequest	Input	SrcFFClk	Training Pattern Request: This is an active high signal that requests training
			patterns be sent out of the Source SPI-4.2 interface. The Source core responds
			by sending out training patterns at the next burst boundary. This signal
			overrides idle requests (IdleRequest) and normal SPI-4.2 data transfers.
			Activating the request for training cycles does not affect the Source FIFO
			contents or the user side operation.

SrcTriStateEn	Input	SrcFFClk	SrcTriStateEn: This is an active high control signal that enables you to tri-state
			the IOB drivers for the following Source core outputs: TDClk, TDat[15:0], and
			TCtl.
			When SrcTriStateEn=0 the outputs are not tri-stated.
			When SrcTriStateEn=1 the outputs are tri-stated.
			Default setting for this signal is disabled (SrcTriStateEn=0.)

34	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

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In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

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Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual bytes with no EOP

Models: UG181

of 16 bytes) with no EOP

• Non-zero value on SrcFFMod when SrcFFEOP is deasserted

SPI-4.2 Lite v4.3 User Guide

UG181 specifications