Sink Core

Table 4-2:SPI-4.2 Control Word Mapping to 64-bit User Interface

R

 

 

Associated SPI-4.2

 

 

Control Word

 

Control

 

Associated Sink FIFO Signals

 

Word bits on RDat

 

 

 

 

 

 

 

(Qualified by RCtl=1)

 

 

 

 

 

 

 

Start of Packet (SOP)

 

RDat[15] = 1, RDat[12] = 1

 

SnkFFSOP,

 

 

 

 

SnkFFAddr[7:0] <== RDat[11:4]

 

 

 

 

 

New Burst (address

 

RDat[15] = 1, RDat[12] = 0

 

SnkFFAddr[7:0] <== RDat[11:4]

change)

 

 

 

 

 

 

 

 

 

End of Packet (EOP,

 

RDat[14:13] = 10

 

SnkFFEOP, SnkFFMod[2:0]

even bytes valid)

 

 

 

When RDat[14:13] = 10:

 

 

 

 

 

 

 

 

Mod = 000 if data bits 63–0 have valid data

 

 

 

 

Mod = 110 if data bits 63–16 have valid data

 

 

 

 

Mod = 100 if data bits 63–32 have valid data

 

 

 

 

Mod = 010 if data bits 63–48 have valid data

 

 

 

 

 

End of Packet (EOP,

 

RDat[14:13] = 11

 

SnkFFEOP, SnkFFMod[2:0]

odd bytes valid)

 

 

 

When RDat[14:13] = 11:

 

 

 

 

 

 

 

 

Mod = 111 if data bits 63–8 have valid data

 

 

 

 

Mod = 101 if data bits 63–24 have valid data

 

 

 

 

Mod = 011 if data bits 63–40 have valid data

 

 

 

 

Mod = 001 if data bits 63–56 have valid data

 

 

 

 

 

End of Packet

 

RDat[14:13] = 01

 

SnkFFErr & SnkFFEOP

(EOP Abort, error

 

 

 

 

condition)

 

 

 

 

 

 

 

 

 

Table 4-3:SPI-4.2 Control Word Mapping to 32-bit User Interface

 

 

 

 

 

 

 

Associated SPI-4.2

 

 

Control Word

 

Control

 

Associated Sink FIFO Signals

 

Word bits on RDat

 

 

 

 

 

 

 

(Qualified by RCtl=1)

 

 

 

 

 

 

 

Start of Packet (SOP)

 

RDat[15] = 1, RDat[12] = 1

 

SnkFFSOP,

 

 

 

 

SnkFFAddr[7:0] <== RDat[11:4]

 

 

 

 

New Burst

 

RDat[15] = 1, RDat[12] = 0

SnkFFAddr[7:0] <== RDat[11:4]

(address change)

 

 

 

 

 

 

 

 

 

End of Packet

 

RDat[14:13] = 10

 

SnkFFEOP, SnkFFMod[1:0]

(EOP, even bytes

 

 

 

When RDat[14:13] = 10:

valid)

 

 

 

 

 

 

MOD = 10 if data bits 31–16 have valid data

 

 

 

 

 

 

 

 

MOD = 00 if data bits 31–0 have valid data

 

 

 

 

 

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

57

UG181 June 27, 2008

Page 56 Page 58
Page 57
Image 57
Xilinx UG181 manual SPI-4.2 Control Word Mapping to 32-bit User Interface
Page 56 Page 58

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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