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UG181 manual 124
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Sink Core Block Diagram
Placement Constraints
Reset
Insertion of DIP2 Errors
Clock Delay in Iserdes
3Sink Fifo Signals Name
Clock Mode
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Image 124
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Chapter 6:
Special Design Considerations
124
www.xilinx.com
SPI-4.2
Lite v4.3 User Guide
UG181 June 27, 2008
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Contents
LogiCORE IP SPI-4.2 Lite
UG181 June 27
SPI-4.2 Lite v4.3 User Guide UG181 June 27
Date Version Revision
Table of Contents
Designing with the Core
Appendix C SPI-4.2 Lite Core Verification
SPI-4.2 Lite v4.3 User Guide
Schedule of Figures
1SPI-4.2 Lite Core in a Typical Link Layer Application
30Addressable Status Fifo Interface 4-Channel Configuration
Schedule of Tables
Generating the Core Designing with the Core
Appendix a SPI-4.2 Lite Control Word
Contents
About This Guide
Conventions
Typographical
Online Document
Conventions
Preface About This Guide
Introduction
About the Core
Recommended Design Experience
Additional Core Resources
Technical Support
Feedback
SPI-4.2 Lite Core
Document
Core Architecture
System Overview
Source Core
Sink Core
Core Architecture
Sink Core Interfaces
Sink Core Interfaces
Sink Core Block Diagram
Sink SPI-4.2 Interface
RCtlN
Sink User Interface
Sink Control and Status Interface
3Sink Fifo Signals Name
Sink Fifo Interface
Core Architecture 3Sink Fifo Signals Name
Sink Core Interfaces
Sink Static Configuration Interface
Number of Complete Training Sequences a
Sink Almost Full Threshold Negate
Sink Clocking Interface
RDClk0 General Purpose
Source Core Interfaces
RDClk0USER This clock
Source SPI-4.2 Interface
Source Core Interfaces
Source User Interface
Domain
Source Control and Status Interface
16 bytes with no EOP
Source Fifo Interface
Name Direction Clock Description Domain
14 Source Status Fifo Signals
Source Static Configuration Interface
Source Status Address
Source Almost Full Threshold Assert
Source Clocking Interface
Source Calendar Period The SrcCalendarM
SysClk0 General Purpose
Domain
Core Architecture
Generating the Core
Core Generator Graphical User Interface
Main Screen
Sink Status Options Screen
Component Name
Core Options
Flow Control
Calendar
Status Interface
Synchronization
Sink Other Options Screen
Fifo Threshold
Clock Mode
Source Status Options Screen
Clocking
Clock Distribution
Source Other Options Screen
Bursting
Burst Mode
Burst Size in Credits
SysClk Distribution
TSClk Distribution
Calendar COE File Format
Understand Signal Pipelining
Designing with the Core
General Design Guidelines
Know the Degree of Difficulty
Recognize Timing Critical Signals
Initializing the SPI-4.2 Lite Core
Keep it Registered
Use Supported Design Flows
Sink Core
Basic Operation
SPI-4.2 Interface
Sink Data Path Example
1SPI-4.2 Interface to the 64-Bit User Interface
SnkFFSOP SnkFFEOP
RCtl
Sink Fifo
SPI-4.2 Control Word Mapping to 32-bit User Interface
Sink Control and Status Signals
Sink Fifo Interface Signals
Sink Fifo Almost Empty
Sink Fifo Empty
Sink Almost Full
Sink Status and Flow Control Signals
Sink Overflow
Sink Calendar Initialization
Initializing the Calendar In-Circuit
Sink Flow Control
7Sink Calendar Initialization
8Typical Flow Control Implementation for 4-Channel System
Sink Status Fifo Interface Example
2,3 None CH 1,2 CH 0,3 CH 0,1,2,3
Sink Status Fifo Status Interface Example
Sink Static Configuration Signals
Insertion of DIP2 Errors
Fifo Almost Full Mode
FifoAFMode and Sink Almost Full
12FIFO Almost Full Mode
Fifo Almost Full Mode 10 or
Sink Data Capture Implementation
Static Alignment
DCM Alignment Implementation Considerations
Synchronization and Start-up
Hunt
Reset
Sync Wait
Error Handling
Sync Data
Sync Train
In-Frame and Out-of-Frame Behavior
Sink Fifo Burst Error
Sink SPI-4.2 Bus Error and Sink Bus Error Status70
EOP Abort Handling
Loss of RDClk
Sequential Payload Control Words
Sink DIP-4 Error Handling
Sequential End-of-Burst Control Words
18Example of Error Flag SnkFFDIP4Err
Source Core
Reserved Control Words
Source Data Path Example
Source Core
22Source Data Path Minimum SOP Spacing Enforced
SrcFFData630 TDat
SPI-4.2 Lite v4.3 User Guide
Transmitting Training Patterns
Source Control and Status Signals
Inserting DIP4 Errors
Transmitting Idle Cycles
Source Fifo Interface Signals
Source Fifo Almost Full
Source Fifo Overflow
24Source Fifo Almost-full Condition
Insertion of DIP-4 Errors
Source Status and Flow Control Signals
Writing to the Source Fifo
Source Calendar Initialization
27Typical User Design Example
Source Flow Control Addressable Status Interface
28Source Calendar Initialization
Addressable Status Fifo Interface Example
29Addressable Status Fifo Interface
30Addressable Status Fifo Interface 4-Channel Configuration
Bank None
Source Flow Control Transparent Status Interface
33Transparent Status Fifo Interface Block Diagram
Source Static Configuration Signals
Source Burst Mode
Source Burst Mode Example
35Example Of Source Burst Mode =
Reset
Source Behavior Before Synchronization
Source Behavior After Synchronization
EOP Abort Insertion
Source Out of Frame
Source DIP-2 Error Handling
Source Pattern Error Handling
Source Status Frame Word Handling
Incorrect Burst Termination
Designing with the Core
Constraining the Core
Overview
Sink Core Required Constraints
Timing Constraints
Maxdelay for Reset
Time Names for Clocks
Timespecs for Clocks
Constraining the Core
Phase Shift for DCM
Clock Delay in Iserdes
DCM and Static Alignment Constraints
Sink Core Required Constraints
Placement Constraints
Placement
IDelayCtrl
Sink Core Optional Constraints
Standards Constraints
IOB Register Packing
Source Core Required Constraints
Area Group Constraints
Timing Ignore Constraints
Timenames for Clocks
Source Core Required Constraints
Inst SysClk LOC = Bank9
Source Core Optional Constraints
Source Core Optional Constraints
Constraints Migration
User Constraints
New Target Region or Device Package
Modifying the UCF File
Target Device
Sink Core
Source Core
Inst TSClk LOC = Bank3
Sink Clocking Options
Special Design Considerations
Embedded Clocking
User Clocking
Special Design Considerations
Sink Clocking Options
Global Clocking
2Sink Core User Clocking Resources Clocking Option
Regional Clocking
3Sink User Clocking Global Clocking
Source Clocking Options
Source Clocking Options
Master Clocking
5Source Clocking Master and Slave Implementation
IOB
8Source Clocking Regional Clocking for SysClk
3SysClk Clocking Resources Clocking Option
Slave Clocking
TSClk Clocking Resources Clocking Option
Multiple Core Implementations
Instantiating Multiple Cores
Creating Top-Level UCF File
Generating the Cores
Multiple Core Implementations
Clocking Considerations
SPI-4.2 Lite v4.3 User Guide 123
124
Simulating and Implementing the Core
Functional Simulation
Generating a Simulation Model
Generating a Simulation Model with Initialized Calendar
Timing Simulation
Simulating and Implementing the Core
Synthesis
Synthesis of Example Design
Synplify
Synthesis
Xilinx Tool Flow
Example Design Script
NGDBuild
Mapping the Design
Generating a Bitstream
Static Timing Analysis
Xilinx Tool Flow
130
SPI-4.2 Lite Control Word
Eops
DIP-4
SPI-4.2 Lite Calendar Programming
Example
Appendix B SPI-4.2 Lite Calendar Programming
SPI-4.2 Lite Core Verification
Appendix C SPI-4.2 Lite Core Verification