Source Core

R

 

 

Read 0

Read 1

Read 2

Read 3

Read 4

Read 5

Read 6

Read 7

Read 8

Read 9

Rd 10

TSClk_GP

 

 

 

 

 

 

 

 

 

 

 

 

SrcEn

 

 

 

 

 

 

 

 

 

 

 

 

SrcStatValid

 

 

 

 

 

 

 

 

 

 

 

 

SrcStatCh[7:0]

DEC

0

2

128

129

9

 

1

 

10

79

16

SrcStat[1:0]

BIN

01

10

00

01

01

10

01

11

00

01

10

Figure 4-34:Transparent Source Status FIFO Interface: 256-channel Configuration

Source Static Configuration Signals

The source static configuration signals are inputs to the core, statically driven to determine the behavior of the core. See Table 2-15, page 38 for a full list of static configuration signals.

Three of the Source Static Configuration signals can be changed in-circuit. There are static registers for SrcBurstLen (synchronous to SrcFFClk), and SrcCalendar_M and SrcCalendar_Len (synchronous to SrcStatClk.) To change these parameters while the core is operational, first deassert SrcEn.

Source Burst Mode

Source Burst Mode (SrcBurstMode) is a static configuration signal that allows one to define how data is transmitted by the Source core. If this signal is set to zero, the Source core transmits data in the FIFO whenever there is a complete credit of data, or when there is an end-of-packet flag (SrcFFEOP.) This is compliant with the transmit operation as defined by the SPI-4.2 OIF specification. If a partial credit is written into the FIFO and then paused, the data in the FIFO will be transmitted up to the last credit boundary.

When SrcBurstMode is set to 1, the Source core only transmits data that is terminated by an EOP or when there is data in the FIFO equal to the maximum burst length defined by the static configuration signal SrcBurstLen. If an incomplete burst is written into the FIFO and paused, then data in the FIFO will be transmitted up to the last burst boundary.

When SrcBurstMode is set to 1, the Source FIFO thresholds (SrcAFThresAssert and SrcAFThresNegate) must be greater than or equal to the burst length (SrcBurstLen). If the FIFO thresholds are set to less than the burst length, the core will force the threshold values to the burst length. This ensures that the FIFO will not report Almost Full before a burst of data has been written into the core.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

93

UG181 June 27, 2008

Page 93
Image 93
Xilinx UG181 manual Source Static Configuration Signals, Source Burst Mode

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.