Xilinx UG181 manual Multiple Core Implementations, Instantiating Multiple Cores

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Chapter 6: Special Design Considerations

Multiple Core Implementations

Using the Xilinx SPI-4.2 Lite Core, a designer can implement multiple SPI-4.2 Lite cores in a single design. Follow the guidelines below to instantiate multiple cores.

Instantiating Multiple Cores

When instantiating multiple cores, the user must instantiate the modules as separate components in the top-level RTL design because there are different netlists for each core.

For example, in VHDL:

Sink core:

first_pl4_lite_snk_top0 : pl4_lite_snk_top1

second_pl4_lite_snk_top0 : pl4_lite_snk_top2

Source core:

first_pl4_lite_src_top0 : pl4_lite_src_top1

second_pl4_lite_src_top0 : pl4_lite_src_top2

Instantiation templates for the cores are available in the coregen project directory and have filename extensions of VHO (for VHDL) and VEO (for Verilog).

If the reference clock (SysClk) can be shared between different Source cores, generate the Source cores with slave clocking to reduce the number of global buffers used in the design. For Virtex-4 or Virtex-5 FPGA designs, regional clocking for the SPI-4.2 Lite Source FIFO Status Clocks (TSClk) can be implemented using regional clocking to further reduce the number of global clock buffers and DCMs used in the design. See “Slave Clocking,” page 119 for more information. If Source cores with slave clocking are used, the separate clocking module (pl4_lite_src_clk) needs to be instantiated in the design. An example clocking module is provided in:

<comp_name>/example_design

The inputs and outputs of the example clock module are:

Inputs: SysClk and TSClk

Outputs: Sysclk0_buf, SysClk180_buf, and TSClk_buf

The outputs of the clocking module, SysClk0_bufg, and SysClk180_bufg can be used to drive the input clocks of the multiple source cores instantiated in the design.

For example:

first_pl4_lite_src_top0 : pl4_lite_src_top1 port map(

................

SysClk180_GBSLV => SysClk180_buf , SysClk0_GSLV => SysClk0_buf ,

...............

) ;

second_pl4_lite_src_top0 : pl4_lite_src_top2 port map (

..............

SysClk180_GBSLV => SysClk180_buf, SysClk0_GBSLV => SysClk0_buf ,

.................

120	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008