Xilinx UG181 Source Core Required Constraints, Area Group Constraints, Timing Ignore Constraints

Models: UG181

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Chapter 5: Constraining the Core

INST

"<sink_instance_name>/U0/pl4_lite_snk_io0/buffer_data/Dat*" DIFF_TERM = TRUE;

INST "<sink_instance_name>/U0/pl4_lite_snk_io0/buffer_data/Ctl" DIFF_TERM = TRUE;

Area Group Constraints

The area group constraints can be used by the user to define a specific placement of the sink core. These constraints are not required for Sink cores that use global clocking distribution but are recommended for Sink cores that use regional clocking distribution.

The following static alignment constraints are used to place the Sink core in one clock region in the example UCF:

* INST <snk_instance_name>/* AREA_GROUP = AG_pl4_lite_snk;

* AREA_GROUP "AG_pl4_lite_snk" RANGE = CLOCKREGION_X0Y4;

Timing Ignore Constraints

If Sink core static configuration signals are driven statically from a register, apply timing ignore attributes (TIG) to the static configuration signals to create proper timing ignore paths. If these are driven statically from a wrapper file, then a TIG is not needed.

In the example UCF file, these constraints are commented out. Add the constraints listed below include them in the design.

NET "SnkAFThresAssert(*)" TIG;

NET "SnkAFThresNegate(*)" TIG;

NET

"FifoAFMode(*)"

TIG;

NET

"NumDip4Errors(*)"

TIG;

NET "NumTrainSequences(*)" TIG;

NET

"RSClkPhase"

TIG;

NET

"RSClkDiv"

TIG;

Source Core Required Constraints

Timing Constraints

Timing constraints are critical for proper operation. The following constraints are provided with the SPI-4.2 Lite core, and the user can modify these constraints to meet their system requirements. In the examples below, the target performance is 340 Mbps. However, the user is responsible for ensuring that any modification to these constraints does not result in paths which are unconstrained.

Timenames for Clocks

The following constraints are for the Source core clocks, and are always required.

NET "SysClk_P" TNM_NET = "SysClk_P";

NET "TSClk" TNM_NET = "TSClk" (for source status I/O type of LVTTL);

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

Page 104
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Xilinx UG181 Source Core Required Constraints, Area Group Constraints, Timing Ignore Constraints, Timenames for Clocks