Sink Other Options Screen, Synchronization

Chapter 3: Generating the Core

Rate

This is the value of static configuration signal RSClkDiv; it selects the frequency of RSClk with respect to RDClk.

Alignment

This is the value of static configuration signal RSClkPhase; it determines whether RStat transitions on the rising or falling edge of RSClk.

Status I/O

This controls whether RStat and RSClk I/O in the generated wrapper file use LVDS or LVTTL I/O.

Sink Other Options Screen

This window contains options that affect the FIFO flags, clocking implementation, status channel behavior, and I/O type.

Synchronization

These options select the default static configuration parameters for core synchronization.

Number of Training Sequences

This is the value of static configuration signal NumTrainSequences; it is the number of training sequences the Sink core must receive on RDat before going in-frame and transiting from framing to status on RStat. The valid range is 1 to 15.

Number of DIP4 Errors

This is the value of static configuration signal NumDIP4Errors; it is the number of consecutive control words with invalid DIP4 values the Sink core must receive on RDat before going out-of-frame and sending framing on RStat. The valid range is 1 to 15.

FIFO Threshold

These options select the default static configuration parameters for Sink core FIFO

Threshold behavior.

Almost Full Assert

This is the value of static configuration signal SnkAFThresAssert; it is the internal FIFO level at which the Sink core will assert SnkFFAlmostFull_n and take the specified flow control action. The valid range is 1–508 and is measured from the full level. For example, if the value chosen is 10, SnkFFAlmostFull_n will be asserted when there are 10 FIFO locations empty.

Almost Full Negate

This is the value of static configuration signal SnkAFThresNegate; it is the internal FIFO level at which the Sink core will deassert SnkFFAlmostFull_n and return RStat behavior

46	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Sink Other Options Screen, Synchronization, Fifo Threshold

Models: UG181