Source Core Interfaces

Table 2-15:Source Static Configuration Signals (Continued)

R

Name

Direction

Range

Description

 

 

 

 

SrcCalendar_M[7:0]

Input

0-255

Source Calendar Period: The SrcCalendar_M

 

 

(effective range 1-256)

parameter sets the number of repetitions of the calendar

 

 

sequence before the DIP-2 parity and framing words are

 

 

 

 

 

 

received.

 

 

 

The Source core implements this parameter as a static

 

 

 

register synchronous to SrcStatClk, and it can be

 

 

 

updated in circuit by first deasserting SrcEn.

 

 

 

Note that the Source Calendar Period equals

 

 

 

SrcCalendar_M + 1. For example, if SrcCalendar_M=22,

 

 

 

the Source Calendar Period will be equal to 23.

 

 

 

 

SrcCalendar_Len[8:0]

Input

0-511

Source Calendar Length: The SrcCalendar_Len

 

 

(effective range 1-512)

parameter sets the length of the calendar sequence.

 

 

 

 

 

 

The Source core implements this parameter as a static

 

 

 

register synchronous to SrcStatClk, and it can be

 

 

 

updated in circuit by first deasserting SrcEn.

 

 

 

Note that the Source Calendar Length equals

 

 

 

SrcCalendar_Len + 1. For example, if

 

 

 

SrcCalendar_Len=15, the Source Calendar Length will

 

 

 

be equal to 16.

 

 

 

 

DataMaxT[15:0]

Static Input

0, 16-65535

Maximum Data-Training Interval: Maximum interval

 

 

 

between scheduling of training sequences on the SPI-

 

 

 

4.2 data path (in SPI-4.2 bus cycles). Note that setting

 

 

 

DataMaxT to zero configures the core to never send

 

 

 

periodic training.

 

 

 

 

AlphaData[7:0]

Static Input

0-255

Data Training Pattern Repetitions: Number of

 

 

 

repetitions of the 20-word data training pattern. Note

 

 

 

that setting AlphaData to zero configures the core to not

 

 

 

periodically send training patterns. In this case, you can

 

 

 

manually send training patterns by asserting the

 

 

 

TrainingRequest command.

 

 

 

 

NumDip2Errors[3:0]

Static Input

1-15

Number of DIP-2 Errors: The Source Interface will go

 

 

Value equal to 0 gets set

out-of-frame (SrcOof asserted) and stop transmitting

 

 

SPI-4.2 data across the data bus after receiving

 

 

to 1

 

 

NumDip2Errors consecutive DIP-2 errors.

 

 

 

 

 

 

 

NumDip2Matches[3:0]

Static Input

1-15

Number of DIP-2 Matches: The Source Interface

 

 

Value equal to 0 gets set

requires NumDip2Matches consecutive DIP-2 matches

 

 

before going in-frame and beginning to transfer SPI-4.2

 

 

to 1

 

 

data across the SPI-4.2 data bus.

 

 

 

 

 

 

 

Source Clocking Interface

The Source core supports two clocking implementations: master clocking and slave clocking. The master clocking configuration provides a complete solution with the clock circuitry embedded within the Source core. The slave clocking configuration allows the clocking scheme to be implemented external to the Source core.

A list of the Source clocks for master clocking and their description is provided in

Table 2-16. Table 2-17defines the Source Core clock status signals, and Table 2-18defines

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

39

UG181 June 27, 2008

Page 38 Page 40
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Image 39
Xilinx UG181 manual Source Clocking Interface, Source Calendar Period The SrcCalendarM
Page 38 Page 40

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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