Xilinx UG181 manual Source SPI-4.2 Interface, Source Core Interfaces

Source Core Interfaces

R

Figure 2-3illustrates the functional modules and signals in each interface—all signals are defined in sections following this illustration.

	SysClk
	SrcEn	SPI-4.2 Lite Source Core
	SrcOof
Control	SrcDIP2Err
and Status	SrcPatternErr
Interface
	IdleRequest
	TrainingRequest
	SrcFFClk
	SrcFFWrEn_n
	SrcFFAddr[7:0]		TDClk
	SrcFFData[63:0] or [31:0]		TDat[15:0]
	SrcFFMod[2:0] or [1:0]		TCtl
FIFO
	SrcFFSOP	Source Data	Source Data
Interface
		FIFO	Transmit
	SrcFFEOP
	SrcFFErr
	SrcFFOverflow_n
	SrcFFAlmostFull_n		SPI4.2
			Source
			Interface
	SrcStatClk
	SrcStatAddr[3:0]
FIFO	SrcStat[31:0]
Status		Source Status
	SrcStatCh[7:0]
Interface		Registers	TSClk
	SrcStatChValid		TStat[1:0]
			Source Status
	SrcCalClk		Receive
Calendar	SrcCalWrEn_n
	SrcCalAddr[8:0]	Source
Control
		Calendar
Interface	SrcCalData[7:0]
	SrcCalDataOut[7:0]
	Static Configuration Signals
		Reset_n
		SrcFifoReset_n
		SrcTriStateEn
	Figure 2-3:Source Core Block Diagram and I/O Interface Signals

Source SPI-4.2 Interface

The SPI-4.2 interface uses LVDS I/O buffers to transmit 16-bit data words. The data words received on the User Interface and the out-of-band control words are multiplexed onto the SPI-4.2 Lite 16-bit databus. The source core supports a 32-bit and 64-bit user interface, which allows it to run at a half (32-bit interface) or quarter (64-bit interface) of the data rate. For example, for a 200 Mbps SPI-4.2 data rate and a 32-bit interface, you can write data into the Source core at 100 MHz. If a 64-bit interface is used, you can write data into the Source core at 50 MHz and maintain the same data rate.

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 31

UG181 June 27, 2008