Source Core Interfaces

R

Figure 2-3illustrates the functional modules and signals in each interface—all signals are defined in sections following this illustration.

 

SysClk

 

 

 

SrcEn

SPI-4.2 Lite Source Core

 

SrcOof

 

 

Control

SrcDIP2Err

 

 

and Status

SrcPatternErr

 

 

Interface

 

 

IdleRequest

 

 

 

 

 

 

TrainingRequest

 

 

 

SrcFFClk

 

 

 

SrcFFWrEn_n

 

 

 

SrcFFAddr[7:0]

 

TDClk

 

SrcFFData[63:0] or [31:0]

 

TDat[15:0]

 

SrcFFMod[2:0] or [1:0]

 

TCtl

FIFO

 

 

SrcFFSOP

Source Data

Source Data

Interface

 

FIFO

Transmit

 

SrcFFEOP

 

 

 

 

SrcFFErr

 

 

 

SrcFFOverflow_n

 

 

 

SrcFFAlmostFull_n

 

SPI4.2

 

 

Source

 

 

 

 

 

 

Interface

 

SrcStatClk

 

 

 

SrcStatAddr[3:0]

 

 

FIFO

SrcStat[31:0]

 

 

Status

Source Status

 

SrcStatCh[7:0]

 

Interface

Registers

TSClk

 

SrcStatChValid

 

TStat[1:0]

 

 

 

 

 

 

Source Status

 

SrcCalClk

 

Receive

Calendar

SrcCalWrEn_n

 

 

SrcCalAddr[8:0]

Source

 

Control

 

 

Calendar

 

Interface

SrcCalData[7:0]

 

 

 

 

SrcCalDataOut[7:0]

 

 

 

Static Configuration Signals

 

 

 

 

Reset_n

 

 

 

SrcFifoReset_n

 

 

 

SrcTriStateEn

 

 

Figure 2-3:Source Core Block Diagram and I/O Interface Signals

Source SPI-4.2 Interface

The SPI-4.2 interface uses LVDS I/O buffers to transmit 16-bit data words. The data words received on the User Interface and the out-of-band control words are multiplexed onto the SPI-4.2 Lite 16-bit databus. The source core supports a 32-bit and 64-bit user interface, which allows it to run at a half (32-bit interface) or quarter (64-bit interface) of the data rate. For example, for a 200 Mbps SPI-4.2 data rate and a 32-bit interface, you can write data into the Source core at 100 MHz. If a 64-bit interface is used, you can write data into the Source core at 50 MHz and maintain the same data rate.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

31

UG181 June 27, 2008

Page 31
Image 31
Xilinx UG181 manual Source SPI-4.2 Interface, Source Core Interfaces

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.