R

Chapter 3: Generating the Core

Status Interface

Status FIFO Interface

This option selects whether the Source core netlist is generated with an addressable or transparent user status interface. For more information, see the “Source Status and Flow Control Signals,” page 85.

Status I/O

This option controls whether the Source core status I/O in the generated wrapper file uses LVDS or LVTTL I/O.

Synchronization

These options select the default static configuration parameters for core synchronization.

Number of DIP2 Matches

This is the value of static configuration signal NumDIP2Matches; it is the number of consecutive valid DIP2 words the Source core must observe on TStat before it goes in frame, deasserts SrcOof, and begins to transmit data on TDat. The valid range is 1 to 15.

Number of DIP2 Errors

This is the value of static configuration signal NumDip2Errors; it is the number of consecutive invalid DIP2 words the Source core must observe on TStat before going out- of-frame. The valid range is 1 to 15.

Source Other Options Screen

This window contains options that affect data burst behavior, FIFO flag behavior, and clocking implementation.

Bursting

This selects the static configuration parameters that determine Source core transmit behavior.

Number of Data Cycles Before Training

This is the value of static configuration signal DataMaxT; it is the approximate number of cycles of data the Source core will transmit on TDat between periodic training sequences. The valid values are 0 and 16 to 65535. A value of 0 indicates that the core will not send periodic training.

Number of Training Patterns During Training

This is the value of static configuration signal AlphaData; it is the number of training patterns the Source core will transmit on TDat each time periodic training is sent. The valid range is from 0 to 255. A value of 0 indicates that the core will not send periodic training.

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UG181 June 27, 2008

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Xilinx UG181 manual Source Other Options Screen, Bursting

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.