Source Core Interfaces

Table 2-14:Source Status FIFO Signals (Continued)

R

Name

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

SrcStatAddr[3:0]

Input

SrcStatClk

Source Status Address:

(Addressable I/F

 

 

For the Addressable Interface, the Source Status Address determines

Only)

 

 

which group of 16-channels gets its status driven onto SrcStat on the

 

 

 

following clock cycle. The address bus is associated with banks of

 

 

 

channels as follows:

 

 

 

Bank 0: SrcStatAddr=0 channel 15-0

 

 

 

Bank 1: SrcStatAddr=1, channel 31-16

 

 

 

Bank 2: SrcStatAddr=2, channel 47-32

 

 

 

...

 

 

 

Bank 15: SrcStatAddr=15 channel 255-240

 

 

 

For the Transparent Interface, this signal is not present.

 

 

 

 

SrcStatCh[7:0]

Output

TSClk_GP

Source Status Channel: The Source Status Channel is an 8-bit bus

 

 

 

containing the channel address that is being updated on the

 

 

 

SrcStatAddr bus in the current clock cycle.

 

 

 

 

SrcStatChValid

Output

TSClk_GP

Source Status Channel Valid: When asserted, Source Status Channel

 

 

 

Valid indicates that the value on SrcStatCh is valid. When the core is

 

 

 

processing DIP-2 or frame words, SrcStatChValid is deasserted. Note

 

 

 

that a transition of the SrcStatChValid from 0 to 1 indicates that the

 

 

 

core has started a new calendar sequence.

 

 

 

 

Source Static Configuration Interface

These signals are inputs to the core that are statically driven by setting them to a constant value in the top-level wrapper file. The SPI-4.2 Lite release includes a wrapper file that has the static configuration signals connected to the values selected in the CORE Generator GUI. Customization of these signals is done using the GUI.

Three of the Source Static Configuration signals can be changed in-circuit. There are static registers for SrcBurstLen (synchronous to SrcFFClk), and SrcCalendar_M and SrcCalendar_Len (synchronous to SrcStatClk.) To change these parameters while the core is operational, you must first deassert SrcEn.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

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UG181 June 27, 2008

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Image 37
Xilinx UG181 manual Source Static Configuration Interface, Source Status Address
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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