Source Almost Full Threshold Assert

Chapter 2: Core Architecture

Note that there are legal values for each of the signals. If the configuration signal is set to an illegal number, the core automatically sets it to the minimum value. Table 2-15defines the Source Static Configuration signals.

Table 2-15:Source Static Configuration Signals

Name	Direction	Range	Description

SrcBurstMode	Static Input	0 or 1	Source Burst Mode: When SrcBurstMode is set to zero,
			the Source core transmits data in the FIFO if the data in
			the FIFO is terminated by an EOP or if there is a
			complete credit of data.
			When SrcBurstMode is set to1, the Source core only
			transmits data that is terminated by an EOP or when
			there is data in the FIFO equal to the maximum burst
			length defined by SrcBurstLen.

SrcBurstLen[5:0]	Input	1-63	Source Burst Length: The Source core automatically
		Values equal to 0 are set	segments packets larger than this parameter into
		Values equal to 0 are set	multiple bursts, which are each SrcBurstLen in length.
		to 1.	multiple bursts, which are each SrcBurstLen in length.
		to 1.	This parameter is defined in credits (16 bytes).
			This parameter is defined in credits (16 bytes).
			The core implements this parameter as a static register
			synchronous to SrcFFClk, and it can be updated in
			circuit by first deasserting SrcEn.

SrcAFThresAssert[8:0]	Static Input	If SrcBurstMode = 0	Source Almost Full Threshold Assert: The
		1 to 508	SrcAFThresAssert parameter specifies the minimum
		Values less than 1 are set	number of empty FIFO locations that exist in the Source
		to 1.	FIFO before the Almost Full signal (SrcFFAlmostFull_n)
		Values greater than 508	is asserted.
		are set to 508.	If SrcBurstMode=0, then SrcAFThresNegate is greater
			If SrcBurstMode=0, then SrcAFThresNegate is greater
		If SrcBurstMode = 1	than or equal to SrcAFThresAssert.
		SrcBurstLen to 508.	If SrcBurstMode=1, then:
		Values less than	If SrcBurstMode=1, then:
		Values less than	(1) SrcAFThresNegate is greater than or equal to
		SrcBurstLen are set to	(1) SrcAFThresNegate is greater than or equal to
		SrcBurstLen are set to	SrcAFThresAssert
		SrcBurstLen.	SrcAFThresAssert
		SrcBurstLen.	(2) SrcAFThresNegate and SrcAFThresAssert are
		Values greater than 508	(2) SrcAFThresNegate and SrcAFThresAssert are
		are set to 508.	greater than or equal to SrcBurstLen

SrcAFThresNegate[8:0]	Static Input	SrcAFThresAssert to	Source Almost Full Threshold Negate: The
		508	SrcAFThresNegate parameter specifies the minimum
		Values less than	number of empty FIFO locations that exist in the Source
		Values less than	FIFO before the Almost Full signal (SrcFFAlmostFull_n)
		SrcAFThresAssert are	FIFO before the Almost Full signal (SrcFFAlmostFull_n)
		SrcAFThresAssert are	is deasserted.
		set to	is deasserted.
		set to
		SrcAFThresAssert.	If SrcBurstMode=0, then:
		Values greater than 508	SrcAFThresNegate is greater than or equal to
		are set to 508.	SrcAFThresAssert.
			If SrcBurstMode=1, then:
			(1) SrcAFThresNegate is greater than or equal to
			SrcAFThresAssert
			(2) SrcAFThresNegate and SrcAFThresAssert are
			greater than or equal to SrcBurstLen

38	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Source Almost Full Threshold Assert

Models: UG181

Source Almost Full Threshold Assert: The

Source Almost Full Threshold Negate: The

SPI-4.2 Lite v4.3 User Guide

UG181 specifications