Sink Fifo Burst Error, EOP Abort Handling

Sink Core

Figure 4-16illustrates back-to-back short packets. In this example there are four channels that are each sending 17-byte packets with a maximum burst of 16 bytes.

1 byte w/ EOP

16 bytes

CH 0

CH 1

CH 2

CH 3

Ch 0	Ch 1	Ch 2	Ch 3	Ch 0	Ch0 EOP
16 bytes	16 bytes	16 bytes	16 bytes	1 byte	1 byte
CTL	CTL	CTL	CTL	CTL	Ch1 CTL

Figure 4-16:Short Packet Support

Sink FIFO Burst Error

When data received on RDat is terminated on a non-credit boundary without an EOP, the Sink core flags this error at the end of the burst by asserting SnkFFBurstErr. SnkFFBurstErr may be used by the user logic to indicate missing EOPs, or incorrectly terminated bursts. In this case the Sink core does not assert SnkFFEOP or SnkFFErr.

EOP Abort Handling

When an EOP abort is received, the Sink core asserts the output flags SnkFFEOP and

SnkFFErr when the packet is terminated. In this case, the Sink core does not assert

SnkFFBurstErr.

Loss of RDClk

When RDClk is not driven, the status signal DCMLost_RDClk is asserted. If RDClk is never present, then the Locked_RDClk signal will never be asserted and the Sink core will not achieve synchronization. If RDClk is present and then lost, then Locked_RDClk will be deasserted and DCMLost_RDClk will be asserted. If DCMLost_RDClk is asserted, it is recommended that you reset the Sink core and re-initiate the synchronization process.

Sink SPI-4.2 Bus Error and Sink Bus Error Status[7:0]

ASink SPI-4.2 Bus Error (SnkBusErr) is an error indication of SPI-4.2 protocol violations or bus errors not associated with a particular data packet. Sink Bus Error Status (SnkBusErrStat[7:0]) triggers simultaneously with SnkBusErr and clarifies which protocol violations have occurred. Each bit of the SnkBusErrStat bus corresponds to one of the following detected conditions.

•SnkBusErrStat[0]: Minimum SOP spacing was violated

•SnkBusErrStat[1]: EOP control word not immediately preceded by data

(Example: EOP followed immediately by another EOP)

•SnkBusErrStat[2]: Payload control word not immediately followed by data

(Example: A payload control word is followed immediately by another payload control word.)

•SnkBusErrStat[3]: DIP4 error received during idle or training patterns

•SnkBusErrStat[4]: Reserved control words received

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

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In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Sink Fifo Burst Error, EOP Abort Handling, Loss of RDClk

Models: UG181