R

Chapter 4: Designing with the Core

Table 4-5:Status Written to Status FIFO Interface

Write Cycle

Status

Status Mask

Starving

Satisfied Status

Address

Status

 

 

 

 

 

 

 

 

0-1

Bank 0

1111.1111.1111.1111

CH 0-15

none

 

 

 

 

 

2

Bank 0

0000.0000.0000.0001

none

CH 0

 

 

 

 

 

3

Bank 1

1000.0000.0000.0000

none

CH 31

 

 

 

 

 

4-5

Bank 2

1111.1111.1111.1111

CH 32-47

none

 

 

 

 

 

6-7

Bank 3

1111.1111.1111.1111

CH 48-63

none

 

 

 

 

 

8-9

Bank 0

1111.0000.0000.0000

none

CH 12-15

 

 

 

 

 

 

 

Write 0 Write 1

Write 2 Write 3

Write 4 Write 5

Write 6 Write 7

Write 8

SnkStatClk

 

 

 

 

 

 

SnkEn

 

 

 

 

 

 

SnkStatAddr[3:0]

BINARY

0000

0001

0010

0011

0000

SnkStatWr_n

 

 

 

 

 

 

 

 

0000.0000.0000.0001

SnkStatMask[15:0]

BINARY

1111.1111.1111.1111

SnkStat[31:0]

HEX

0000.0000

 

 

0000.0002

1000.0000.0000.0000

1111.1111.1111.1111 1111.0000.0000.0000

0000.0000AA00.0000

8000.0000

Figure 4-10:Sink Status FIFO Interface Example: 64-channel Configuration

Sink Status FIFO Status Interface: Example 3

This example illustrates status received on the user interface and written to the SPI-4.2 bus. Figure 4-11shows a RStat waveform for a calendar length of four (SnkCalendar_Len=3) and calendar repetition value of one (SnkCalendar_M=0). Note that FIFO status information is periodic, repeating the sequence of a framing pattern (11), a repeated set of FIFO status words (SnkCalendar_M + 1 times) in accordance with the programmed calendar order, and a DIP-2 value. The programmed calendar sequence is channel 0, 1, 2, 3, and the following RStat[1:0] sequence is illustrated:

Sequence #: CH0, CH1, CH2, CH3

Sequence 1: 10, 00, 00, 00

Sequence 2: 10, 00, 10, 10

Sequence 3: 10, 10, 10, 10

66

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

Page 66
Image 66
Xilinx UG181 manual Sink Status Fifo Status Interface Example

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.