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Appendix B

SPI-4.2 Lite Calendar Programming

This appendix lists examples that describe how to program calendars for the Source Status FIFO and Sink Status FIFO of the SPI-4.2 Lite core.

Overview

In a typical application, the calendars for the Source FIFO status and Sink FIFO status will be programmed identically. In this case, the user may choose to combine the Rx and Tx calendar input signals (clocks, write enable, address, and data) and drive them from the same Source. This will let the user initialize the Rx and Tx calendars simultaneously.

In the SPI-4.2 Lite core, the notion of calendar replaces the polling/packet (or cell) available functionality in previous POS-PHY and UTOPIA specifications. In these preceding standards, the Link or ATM Layer polls the channels and the Physical Layer responds with a “packet available” or “cell available” status. In SPI-4.2 Lite, the polling is replaced by FIFO status reporting of each channel in a specific order that is controlled by the calendar. In this implementation, as illustrated in the examples below, the calendar is inserted as a table containing channel numbers that is initialized at power-up. Consider the following examples.

Example 1

In a channelized OC-192 with 192 STS-1 channels, all channels have equal bandwidth and should report their status with equal frequency. In this case, the Calendar Length is 192 (Calendar_Len=191) and the Calendar entries are: 0, 1, 2, …, 191.

Example 2

In a channelized OC-192 with three STS-48 channels (0, 1, and 2) and 4 STS-12 channels (3, 4, 5, and 6), the three STS-48 channels have four times the bandwidth of the 4 STS-12 channels. Therefore, the 3 high-speed channels should report their status 4 times as frequently as the low-speed channels in one Calendar cycle. In this case, the Calendar Length is 16 (Calendar_Len=15) and the Calendar entries are: 0, 1, 2, 3, 0, 1, 2, 4, 0, 1, 2, 5, 0, 1, 2, 6.

Once the Calendar is programmed, the user circuitry updates FIFO status in the dual-port RAM in the Sink block and the SPI-4.2 Lite core sends the updated status information in the order programmed in the calendar. Likewise, in the Source block, the SPI-4.2 Lite core receives the FIFO status information according to the order programmed in the calendar and writes the status in the dual-port RAM to be read by the user circuitry.

SPI-4.2 Lite v4.3 User Guide

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UG181 specifications

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