Sink Core Interfaces

Sink Status and Flow Control Interface (Calendar Control and Status FIFO)

The Sink Status and Flow Control interface enables you to send flow control data on the SPI-4.2 Interface. The status information is sent based on the channel order and channel frequency defined in the programmable calendar. Table 2-4and Table 2-5define the calendar interface and status FIFO interface signals.

Table 2-4:Sink Calendar Control Signals

Name	Direction	Clock	Description
Name	Direction	Domain	Description
		Domain

SnkCalClk	Input	n/a	Sink Calendar Clock: All Sink calendar signals are synchronous to
			this clock.

SnkCalWrEn_n	Input	SnkCalClk	Sink Calendar Write Enable: When this signal is asserted (active
			low), the Sink Calendar is written with the data on the SnkCalData
			bus on the rising edge of SnkCalClk. When the signal is deasserted,
			the Sink Calendar data can be read on SnkCalDataOut.

SnkCalAddr[8:0]	Input	SnkCalClk	Sink Calendar Address: When SnkCalWrEn_n is asserted, this bus
			indicates the calendar address to which the data on SnkCalData is
			written. When SnkCalWrEn_n is deasserted, this bus indicates the
			calendar address from which the channel number on SnkCalDataOut
			is driven.

SnkCalData[7:0]	Input	SnkCalClk	Sink Calendar Data: This bus contains the channel number to write
			into the calendar buffer when SnkCalWrEn_n is enabled. The channel
			numbers written into the calendar indicate the order that status is
			sent on RStat.

SnkCalDataOut[7:0]	Output	SnkCalClk	Sink Calendar Data Output: This bus contains the channel number
			that is read from the calendar buffer when SnkCalWrEn_n is disabled.
			The channel numbers read from the calendar indicate the order that
			status is sent on RStat.

Table 2-5:Sink Status FIFO Signals

Name	Direction	Clock	Description
Name	Direction	Domain	Description
		Domain

SnkStatClk	Input	n/s	Sink Status Clock: All Sink Status write signals are synchronous to
			this clock.

SnkStat[31:0]	Input	SnkStatClk	Sink Status Bus: This 32-bit bus is used to write status information
			into the Status FIFO. You can write the status for 16 channels each
			clock cycle.
			The 16-channel status that are accessed simultaneously are grouped
			in the following manner: channels 15 to 0, channels 31 to 16, channels
			47 to 32, . . . , channels 255 to 239.

SnkDIP2ErrRequest	Input	SnkStatClk	Sink DIP2 Error Request: This is an active high signal that requests
			an incorrect DIP-2 to be sent out of the RStat bus. When this signal is
			asserted, Sink Status FIFO responds by inverting the next DIP2 value
			that it transmits.

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

UG181 specifications

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Xilinx UG181 manual Sink Core Interfaces

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