Xilinx UG181 manual 22Source Data Path Minimum SOP Spacing Enforced

Models: UG181

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Chapter 4: Designing with the Core

containing the end-of-packet information for channel 2. Finally, the start-of-packet and address information for channel 3 are sent in the payload control word (C3).

If the payload control words did not contain SOP indications (such as payload resumes), the Source core would not be required to enforce minimum SOP spacing. The Source core will then pack the EOP and Payload Control word into a single cycle and will not insert idle cycles. This behavior is illustrated in Figure 4-23.

SrcFFClk

 

 

 

SrcFFWrEn_n

 

 

 

SrcFFAddr

CH1

CH2

CH3

SrcFFData

1A 1B -- --

2A 2B 2C --

3A 3B -- --

SrcFFMod

100

110

100

SrcFFSOP

 

 

 

SrcFFEOP

 

 

 

TDClk_P

 

 

 

TDat_P

 

 

C1 1A 1B I I I I I C2 2A 2B 2C I I I I C3

TCtl_P

 

 

 

Figure 4-22:Source Data Path - Minimum SOP Spacing Enforced

SrcFFClk

 

 

 

SrcFFWrEn_n

 

 

 

SrcFFAddr

CH1

CH2

CH3

SrcFFData

1A 1B -- --

2A 2B 2C --

3A 3B -- --

SrcFFMod

100

110

100

SrcFFSOP

 

 

 

SrcFFEOP

 

 

 

TDClk_P

 

 

 

TDat_P

 

 

C1 1A 1B C2 2A 2B 2C C3

TCtl_P

 

 

 

Figure 4-23:Source Data Path - Short Packet Transfers

The Source core formats the data to be written onto the SPI-4.2 Lite bus (TDat). Table 4-6shows an example of the formatting that this block does with the data read-out of the Source FIFO (control words are binary and payload transfers are hexadecimal). When an SOP is read out of the FIFO, the following 16-bit word transfer sent on the SPI-4.2 data bus is an SOP control word. This example shows the receipt of an SOP for channel 2 and two

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

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Xilinx UG181 manual 22Source Data Path Minimum SOP Spacing Enforced