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Sink Core Block Diagram
Placement Constraints
Reset
Insertion of DIP2 Errors
Clock Delay in Iserdes
3Sink Fifo Signals Name
Clock Mode
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Chapter 2:
Core Architecture
42
www.xilinx.com
SPI-4.2
Lite v4.3 User Guide
UG181 June 27, 2008
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Contents
LogiCORE IP SPI-4.2 Lite
UG181 June 27
SPI-4.2 Lite v4.3 User Guide UG181 June 27
Date Version Revision
Table of Contents
Designing with the Core
Appendix C SPI-4.2 Lite Core Verification
SPI-4.2 Lite v4.3 User Guide
Schedule of Figures
1SPI-4.2 Lite Core in a Typical Link Layer Application
30Addressable Status Fifo Interface 4-Channel Configuration
Schedule of Tables
Generating the Core Designing with the Core
Appendix a SPI-4.2 Lite Control Word
Contents
About This Guide
Conventions
Typographical
Online Document
Conventions
Preface About This Guide
Recommended Design Experience
Introduction
About the Core
Additional Core Resources
SPI-4.2 Lite Core
Technical Support
Feedback
Document
Core Architecture
System Overview
Sink Core
Source Core
Core Architecture
Sink Core Interfaces
Sink Core Interfaces
Sink Core Block Diagram
Sink SPI-4.2 Interface
RCtlN
Sink User Interface
Sink Control and Status Interface
3Sink Fifo Signals Name
Sink Fifo Interface
Core Architecture 3Sink Fifo Signals Name
Sink Core Interfaces
Sink Static Configuration Interface
Number of Complete Training Sequences a
Sink Almost Full Threshold Negate
Sink Clocking Interface
RDClk0 General Purpose
Source Core Interfaces
RDClk0USER This clock
Source SPI-4.2 Interface
Source Core Interfaces
Source User Interface
Domain
Source Control and Status Interface
16 bytes with no EOP
Source Fifo Interface
Name Direction Clock Description Domain
14 Source Status Fifo Signals
Source Static Configuration Interface
Source Status Address
Source Almost Full Threshold Assert
Source Clocking Interface
Source Calendar Period The SrcCalendarM
SysClk0 General Purpose
Domain
Core Architecture
Generating the Core
Core Generator Graphical User Interface
Component Name
Main Screen
Sink Status Options Screen
Core Options
Calendar
Flow Control
Status Interface
Sink Other Options Screen
Synchronization
Fifo Threshold
Clocking
Clock Mode
Source Status Options Screen
Clock Distribution
Source Other Options Screen
Bursting
SysClk Distribution
Burst Mode
Burst Size in Credits
TSClk Distribution
Calendar COE File Format
General Design Guidelines
Understand Signal Pipelining
Designing with the Core
Know the Degree of Difficulty
Keep it Registered
Recognize Timing Critical Signals
Initializing the SPI-4.2 Lite Core
Use Supported Design Flows
SPI-4.2 Interface
Sink Core
Basic Operation
Sink Data Path Example
1SPI-4.2 Interface to the 64-Bit User Interface
SnkFFSOP SnkFFEOP
RCtl
Sink Fifo
SPI-4.2 Control Word Mapping to 32-bit User Interface
Sink Control and Status Signals
Sink Fifo Interface Signals
Sink Fifo Almost Empty
Sink Fifo Empty
Sink Almost Full
Sink Status and Flow Control Signals
Sink Overflow
Sink Calendar Initialization
Initializing the Calendar In-Circuit
Sink Flow Control
7Sink Calendar Initialization
8Typical Flow Control Implementation for 4-Channel System
Sink Status Fifo Interface Example
2,3 None CH 1,2 CH 0,3 CH 0,1,2,3
Sink Status Fifo Status Interface Example
Fifo Almost Full Mode
Sink Static Configuration Signals
Insertion of DIP2 Errors
FifoAFMode and Sink Almost Full
12FIFO Almost Full Mode
Static Alignment
Fifo Almost Full Mode 10 or
Sink Data Capture Implementation
DCM Alignment Implementation Considerations
Synchronization and Start-up
Reset
Hunt
Sync Wait
Sync Train
Error Handling
Sync Data
In-Frame and Out-of-Frame Behavior
EOP Abort Handling
Sink Fifo Burst Error
Sink SPI-4.2 Bus Error and Sink Bus Error Status70
Loss of RDClk
Sink DIP-4 Error Handling
Sequential Payload Control Words
Sequential End-of-Burst Control Words
18Example of Error Flag SnkFFDIP4Err
Source Core
Reserved Control Words
Source Data Path Example
Source Core
22Source Data Path Minimum SOP Spacing Enforced
SrcFFData630 TDat
SPI-4.2 Lite v4.3 User Guide
Transmitting Training Patterns
Inserting DIP4 Errors
Source Control and Status Signals
Transmitting Idle Cycles
Source Fifo Interface Signals
Source Fifo Almost Full
Source Fifo Overflow
24Source Fifo Almost-full Condition
Source Status and Flow Control Signals
Insertion of DIP-4 Errors
Writing to the Source Fifo
Source Calendar Initialization
27Typical User Design Example
Source Flow Control Addressable Status Interface
28Source Calendar Initialization
Addressable Status Fifo Interface Example
29Addressable Status Fifo Interface
30Addressable Status Fifo Interface 4-Channel Configuration
Bank None
Source Flow Control Transparent Status Interface
33Transparent Status Fifo Interface Block Diagram
Source Static Configuration Signals
Source Burst Mode
Source Burst Mode Example
35Example Of Source Burst Mode =
Reset
EOP Abort Insertion
Source Behavior Before Synchronization
Source Behavior After Synchronization
Source Out of Frame
Source Status Frame Word Handling
Source DIP-2 Error Handling
Source Pattern Error Handling
Incorrect Burst Termination
Designing with the Core
Sink Core Required Constraints
Constraining the Core
Overview
Timing Constraints
Timespecs for Clocks
Maxdelay for Reset
Time Names for Clocks
Constraining the Core
DCM and Static Alignment Constraints
Phase Shift for DCM
Clock Delay in Iserdes
Sink Core Required Constraints
Placement Constraints
Placement
Standards Constraints
IDelayCtrl
Sink Core Optional Constraints
IOB Register Packing
Timing Ignore Constraints
Source Core Required Constraints
Area Group Constraints
Timenames for Clocks
Source Core Required Constraints
Inst SysClk LOC = Bank9
Source Core Optional Constraints
Source Core Optional Constraints
User Constraints
Constraints Migration
New Target Region or Device Package
Sink Core
Modifying the UCF File
Target Device
Source Core
Inst TSClk LOC = Bank3
Special Design Considerations
Sink Clocking Options
Embedded Clocking
User Clocking
Special Design Considerations
Global Clocking
Sink Clocking Options
2Sink Core User Clocking Resources Clocking Option
Regional Clocking
3Sink User Clocking Global Clocking
Source Clocking Options
Source Clocking Options
Master Clocking
5Source Clocking Master and Slave Implementation
IOB
8Source Clocking Regional Clocking for SysClk
Slave Clocking
3SysClk Clocking Resources Clocking Option
TSClk Clocking Resources Clocking Option
Multiple Core Implementations
Instantiating Multiple Cores
Generating the Cores
Creating Top-Level UCF File
Multiple Core Implementations
Clocking Considerations
SPI-4.2 Lite v4.3 User Guide 123
124
Generating a Simulation Model
Simulating and Implementing the Core
Functional Simulation
Generating a Simulation Model with Initialized Calendar
Timing Simulation
Simulating and Implementing the Core
Synplify
Synthesis
Synthesis of Example Design
Synthesis
NGDBuild
Xilinx Tool Flow
Example Design Script
Mapping the Design
Static Timing Analysis
Generating a Bitstream
Xilinx Tool Flow
130
SPI-4.2 Lite Control Word
Eops
DIP-4
SPI-4.2 Lite Calendar Programming
Example
Appendix B SPI-4.2 Lite Calendar Programming
SPI-4.2 Lite Core Verification
Appendix C SPI-4.2 Lite Core Verification