Sink User Interface

Chapter 2: Core Architecture

The Sink User Interface includes all signals other than those on the SPI-4.2 Interface. The high-performance logic on the Sink back-end enables the user interface to run at higher frequencies than the SPI-4.2 Interface. This is sometimes required if a large percentage of the traffic consists of small packets.

The User Interface is subdivided into five smaller interfaces. Each of these interfaces are presented in detail below:

•Control and Status Interface: The signals of this interface apply to the operation of the Sink core.

•FIFO Interface: The signals of this interface allow you to access data received on the SPI-4.2 Interface.

•Status and Flow Control Interface: The signals of this interface send flow control information on the SPI-4.2 Interface.

•Static Configuration Interface: The signals of this interface allow you to configure the core.

•Clocking Interface: The signals of this interface report the status of the clocks and include the general purpose clocks.

Sink Control and Status Interface

The Sink core control and status signals either control the operation of the entire Sink core or provide status information that is not associated with a particular channel (port) or packet. Table 2-2defines the Sink control and status signals.

Table 2-2:Sink Control and Status Signals

Name	Direction	Clock	Description
Name	Direction	Domain	Description
		Domain

Reset_n	Input	n/a	Reset: Active Low signal that asynchronously initializes internal flip-flops,
			registers, and counters. When Reset_n is asserted, the Sink core will go out
			of frame and the entire data path is cleared (including the FIFO). The Sink
			core will also assert SnkOof, and deassert SnkBusErr and SnkTrainValid.
			When Reset_n is asserted, the Sink core will transmit framing "11" on RStat
			and continue to drive RSClk.
			Following the deassertion of Reset_n, the sink calendar should be
			programmed if the calendar is initialized in-circuit.

SnkFifoReset_n	Input	SnkFFClk	Sink FIFO Reset: Active low signal enables you to reset the Sink FIFO and
			the associated data path logic. This enables the FIFO to be cleared while
			remaining in frame.
			Coming out of SnkFifoReset_n, the Sink core will discard all data on the SPI-
			4.2 interface until a valid SOP control word is received.

SnkEn	Input	SnkStatClk	Sink Enable: Active high signal that enables the Sink core. When SnkEn is
			deasserted, the Sink core will go out of frame and will not store any
			additional data in the FIFO. The current contents of the FIFO remain intact.
			The Sink core will also assert SnkOof, and deassert SnkBusErr and
			SnkTrainValid. When SnkEn is deasserted, the Sink core will transmit
			framing "11" on RStat and continue to drive RSClk.

22	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Sink User Interface, Sink Control and Status Interface

Models: UG181

Chapter 2: Core Architecture