R

Chapter 4: Designing with the Core

Table 4-3:SPI-4.2 Control Word Mapping to 32-bit User Interface (Continued)

 

Associated SPI-4.2

 

Control Word

Control

Associated Sink FIFO Signals

Word bits on RDat

 

 

 

(Qualified by RCtl=1)

 

 

 

 

End of Packet

RDat[14:13] = 11

SnkFFEOP, SnkFFMod[1:0]

(EOP, odd bytes

 

When RDat[14:13] = 11:

valid)

 

 

MOD = 11 if data bits 31–8 have valid data

 

 

 

 

MOD = 01 if data bits 31–24 have valid data

 

 

 

End of Packet

RDat[14:13] = 01

SnkFFErr & SnkFFEOP

(EOP Abort, error

 

 

condition)

 

 

 

 

 

Sink User Interface

The Sink User Interface includes all the signals to the core other than those on the SPI-4.2 Interface (See “SPI-4.2 Interface,” page 53). The high performance Sink back-end enables the user interface to run at higher frequencies than the SPI-4.2 Interface. This is sometimes required if a large percentage of traffic consists of small packets.

The user interface has three major sections:

•Control and Status Signals: These signals apply to the operation of the entire Sink core

•FIFO Interface Signals: These signals allow you to access the data received on the SPI-4.2 Interface

•Status and Flow Control Signals: These signals are used to send flow control information on the SPI-4.2 Interface

Sink Control and Status Signals

These signals control the operation of the entire Sink core or provide status information not associated with a specific channel (port) or packet. The Sink control and status signals are defined in Table 2-2.

There are six global status signals:

•Sink Out-of-Frame(SnkOof) is asserted active high whenever the core loses synchronization with the SPI-4.2 interface.

•Sink Bus Error Status (SnkBusErrStat[7:0]) is asserted when a SPI-4.2 protocol violation or an error not associated with a specific data packet occurs. Each bit of the SnkBusErrStat bus corresponds to one of the following conditions:

♦SnkBusErrStat[0]: Minimum SOP spacing was violated.

♦SnkBusErrStat[1]: EOP control word not immediately preceded by data.

(Example: EOP followed immediately by another EOP)

♦SnkBusErrStat[2]: Payload control word not immediately followed by data.

(Example: A payload control word is followed immediately by another payload control word.)

♦SnkBusErrStat[3]: DIP4 error received during idles or training patterns.

♦SnkBusErrStat[4]: Reserved control words received.

58

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

Page 57 Page 59
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Image 58
Xilinx UG181 manual Sink User Interface, Sink Control and Status Signals
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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