Source Core

R

64-bit words from the Source FIFO are transmitted on the SPI-4.2 data bus. The DIP-4 parity depends on this control word and any proceeding transfer; therefore, it is left as “pppp” (shown in the 13th TDClk clock cycle).

Following this example are two tables showing the mapping between the packet status signals on the user interface and SPI-4.2 control words for a 32-bit user interface (Table 4-7) and for a 64-bit user interface (Table 4-8).

Table 4-6:Example of Formatting Source FIFO Data for a 64-bit User Interface

Data Written to the

SrcFFClk

 

Data Transmitted on the

 

TDClk

Source FIFO

FIFO Control Bit

SPI-4.2 Interface

TCtl

Cycle

cycle

(SrcFFData[63:0])

 

(TDat [15:0])

 

 

 

 

 

 

 

 

 

 

 

SrcFFData[63:0] =

1

SrcFFSOP = 1

N/A

N/A

n

[F1E2.D3C4.B5A6.9F8E]

 

SrcFFEOP = 0

 

 

 

 

SOP

1

n+1

 

 

SrcFFMOD = 000

 

 

b:[1001.0000.0010.pppp]

 

 

 

 

SrcFFAddr = 0000.0010

 

 

 

 

 

 

 

 

 

SPI-4.2 Lite Word 0 (P0)

0

n+2

 

 

SrcFFErr = 0

 

 

F1E2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI-4.2 Lite Word 1 (P1)

0

n+3

 

 

 

D3C4

 

 

 

 

 

 

 

 

SrcFFData[63:0] =

2

SrcFFSOP= 0

SPI-4.2 Lite Word 2 (P2)

0

n+4

[1F2E.3D4C.5B6A.F9E8]

 

SrcFFEOP = 0

B5A6

 

 

 

 

SrcFFMOD = 000

 

 

 

 

 

SPI-4.2 Lite Word 3 (P3)

0

n+5

 

 

SrcFFAddr = 0000.0010

 

 

9F8E

 

 

 

 

SrcFFErr = 0

 

 

 

 

 

 

 

 

 

SPI-4.2 Lite Word 4 (P4)

0

n+6

 

 

 

 

 

 

1F2E

 

 

 

 

 

 

 

 

 

 

 

SPI-4.2 Lite Word 5 (P5)

0

n+7

 

 

 

3D4C

 

 

 

 

 

 

 

 

SrcFFData[63:0]

3

SrcFFSOP= 0

SPI-4.2 Lite Word 6 (P6)

0

n+8

[ABCD.1200.0000.0000]

 

SrcFFEOP=1

5B6A

 

 

 

 

SrcFFMOD = 011

 

 

 

 

 

SPI-4.2 Lite Word 7 (P7)

0

n+9

 

 

SrcFFAddr = 0000.0010

 

 

F9E8

 

 

 

 

SrcFFErr = 0

 

 

 

 

 

 

 

 

 

SPI-4.2 Lite Word 8 (P8)

0

n+10

 

 

 

 

 

 

ABCD

 

 

 

 

 

 

 

 

 

 

 

SPI-4.2 Lite Word 9 (P9)

0

n+11

 

 

 

1200

 

 

 

 

 

 

 

 

 

4

 

EOP / MOD

1

n+12

 

 

 

b:[0110.0000.0010.pppp]

 

 

 

 

 

 

 

 

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

79

UG181 June 27, 2008

Page 79
Image 79
Xilinx UG181 manual SrcFFData630 TDat

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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