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Xilinx UG181 manual SrcFFData630 TDat

Models: UG181

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Source Core

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64-bit words from the Source FIFO are transmitted on the SPI-4.2 data bus. The DIP-4 parity depends on this control word and any proceeding transfer; therefore, it is left as “pppp” (shown in the 13th TDClk clock cycle).

Following this example are two tables showing the mapping between the packet status signals on the user interface and SPI-4.2 control words for a 32-bit user interface (Table 4-7) and for a 64-bit user interface (Table 4-8).

Table 4-6:Example of Formatting Source FIFO Data for a 64-bit User Interface

	Data Written to the	SrcFFClk		Data Transmitted on the		TDClk
	Source FIFO	SrcFFClk	FIFO Control Bit	SPI-4.2 Interface	TCtl	TDClk
	Source FIFO	Cycle	FIFO Control Bit	SPI-4.2 Interface	TCtl	cycle
	(SrcFFData[63:0])	Cycle		(TDat [15:0])		cycle
	(SrcFFData[63:0])			(TDat [15:0])

	SrcFFData[63:0] =	1	SrcFFSOP = 1	N/A	N/A	n
	[F1E2.D3C4.B5A6.9F8E]		SrcFFEOP = 0
	[F1E2.D3C4.B5A6.9F8E]		SrcFFEOP = 0	SOP	1	n+1
			SrcFFMOD = 000	SOP	1	n+1
			SrcFFMOD = 000	b:[1001.0000.0010.pppp]
			SrcFFAddr = 0000.0010	b:[1001.0000.0010.pppp]

				SPI-4.2 Lite Word 0 (P0)	0	n+2
			SrcFFErr = 0	SPI-4.2 Lite Word 0 (P0)	0	n+2
			SrcFFErr = 0	F1E2
				F1E2

				SPI-4.2 Lite Word 1 (P1)	0	n+3
				D3C4

	SrcFFData[63:0] =	2	SrcFFSOP= 0	SPI-4.2 Lite Word 2 (P2)	0	n+4
	[1F2E.3D4C.5B6A.F9E8]		SrcFFEOP = 0	B5A6
			SrcFFMOD = 000
			SrcFFMOD = 000	SPI-4.2 Lite Word 3 (P3)	0	n+5
			SrcFFAddr = 0000.0010	SPI-4.2 Lite Word 3 (P3)	0	n+5
			SrcFFAddr = 0000.0010	9F8E
			SrcFFErr = 0	9F8E

				SPI-4.2 Lite Word 4 (P4)	0	n+6
				SPI-4.2 Lite Word 4 (P4)	0	n+6
				1F2E

				SPI-4.2 Lite Word 5 (P5)	0	n+7
				3D4C

	SrcFFData[63:0]	3	SrcFFSOP= 0	SPI-4.2 Lite Word 6 (P6)	0	n+8
	[ABCD.1200.0000.0000]		SrcFFEOP=1	5B6A
			SrcFFMOD = 011
			SrcFFMOD = 011	SPI-4.2 Lite Word 7 (P7)	0	n+9
			SrcFFAddr = 0000.0010	SPI-4.2 Lite Word 7 (P7)	0	n+9
			SrcFFAddr = 0000.0010	F9E8
			SrcFFErr = 0	F9E8

				SPI-4.2 Lite Word 8 (P8)	0	n+10
				SPI-4.2 Lite Word 8 (P8)	0	n+10
				ABCD

				SPI-4.2 Lite Word 9 (P9)	0	n+11
				1200

		4		EOP / MOD	1	n+12
				b:[0110.0000.0010.pppp]

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual SrcFFData630 TDat

Contents

UG181 June 27 LogiCORE IP SPI-4.2 LiteDate Version Revision SPI-4.2 Lite v4.3 User Guide UG181 June 27Table of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide 1SPI-4.2 Lite Core in a Typical Link Layer Application Schedule of Figures30Addressable Status Fifo Interface 4-Channel Configuration Generating the Core Designing with the Core Schedule of TablesAppendix a SPI-4.2 Lite Control Word About This Guide ContentsTypographical ConventionsConventions Online DocumentPreface About This Guide Additional Core Resources IntroductionAbout the Core Recommended Design ExperienceDocument Technical SupportFeedback SPI-4.2 Lite CoreSystem Overview Core ArchitectureSource Core Sink CoreCore Architecture Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram RCtlN Sink SPI-4.2 InterfaceSink Control and Status Interface Sink User InterfaceSink Fifo Interface 3Sink Fifo Signals NameCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate RDClk0 General Purpose Sink Clocking InterfaceRDClk0USER This clock Source Core InterfacesSource Core Interfaces Source SPI-4.2 InterfaceDomain Source User InterfaceSource Control and Status Interface 16 bytes with no EOP Name Direction Clock Description Domain Source Fifo Interface14 Source Status Fifo Signals Source Status Address Source Static Configuration InterfaceSource Almost Full Threshold Assert Source Calendar Period The SrcCalendarM Source Clocking InterfaceSysClk0 General Purpose Domain Core Architecture Core Generator Graphical User Interface Generating the CoreCore Options Main ScreenSink Status Options Screen Component NameFlow Control CalendarStatus Interface Synchronization Sink Other Options ScreenFifo Threshold Clock Distribution Clock ModeSource Status Options Screen ClockingBursting Source Other Options ScreenTSClk Distribution Burst ModeBurst Size in Credits SysClk DistributionCalendar COE File Format Know the Degree of Difficulty Understand Signal PipeliningDesigning with the Core General Design GuidelinesUse Supported Design Flows Recognize Timing Critical SignalsInitializing the SPI-4.2 Lite Core Keep it RegisteredSink Data Path Example Sink CoreBasic Operation SPI-4.2 Interface1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP Sink Fifo RCtlSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Almost Empty Sink Fifo Interface SignalsSink Almost Full Sink Fifo EmptySink Overflow Sink Status and Flow Control SignalsInitializing the Calendar In-Circuit Sink Calendar Initialization7Sink Calendar Initialization Sink Flow Control8Typical Flow Control Implementation for 4-Channel System 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3 Sink Status Fifo Interface ExampleSink Status Fifo Status Interface Example FifoAFMode and Sink Almost Full Sink Static Configuration SignalsInsertion of DIP2 Errors Fifo Almost Full Mode12FIFO Almost Full Mode DCM Alignment Implementation Considerations Fifo Almost Full Mode 10 orSink Data Capture Implementation Static AlignmentSynchronization and Start-up Hunt ResetSync Wait In-Frame and Out-of-Frame Behavior Error HandlingSync Data Sync TrainLoss of RDClk Sink Fifo Burst ErrorSink SPI-4.2 Bus Error and Sink Bus Error Status70 EOP Abort HandlingSequential Payload Control Words Sink DIP-4 Error HandlingSequential End-of-Burst Control Words 18Example of Error Flag SnkFFDIP4Err Reserved Control Words Source CoreSource Core Source Data Path Example22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Source Control and Status Signals Inserting DIP4 ErrorsTransmitting Idle Cycles Source Fifo Almost Full Source Fifo Interface Signals24Source Fifo Almost-full Condition Source Fifo OverflowInsertion of DIP-4 Errors Source Status and Flow Control SignalsWriting to the Source Fifo 27Typical User Design Example Source Calendar Initialization28Source Calendar Initialization Source Flow Control Addressable Status Interface29Addressable Status Fifo Interface Addressable Status Fifo Interface Example30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Burst Mode Source Static Configuration Signals35Example Of Source Burst Mode = Source Burst Mode ExampleReset Source Out of Frame Source Behavior Before SynchronizationSource Behavior After Synchronization EOP Abort InsertionIncorrect Burst Termination Source DIP-2 Error HandlingSource Pattern Error Handling Source Status Frame Word HandlingDesigning with the Core Timing Constraints Constraining the CoreOverview Sink Core Required ConstraintsConstraining the Core Maxdelay for ResetTime Names for Clocks Timespecs for ClocksSink Core Required Constraints Phase Shift for DCMClock Delay in Iserdes DCM and Static Alignment ConstraintsPlacement Placement ConstraintsIOB Register Packing IDelayCtrlSink Core Optional Constraints Standards ConstraintsTimenames for Clocks Source Core Required ConstraintsArea Group Constraints Timing Ignore ConstraintsSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsConstraints Migration User ConstraintsNew Target Region or Device Package Source Core Modifying the UCF FileTarget Device Sink CoreInst TSClk LOC = Bank3 Sink Clocking Options Special Design ConsiderationsEmbedded Clocking Special Design Considerations User ClockingSink Clocking Options Global Clocking2Sink Core User Clocking Resources Clocking Option 3Sink User Clocking Global Clocking Regional ClockingSource Clocking Options Source Clocking Options5Source Clocking Master and Slave Implementation Master ClockingIOB 8Source Clocking Regional Clocking for SysClk 3SysClk Clocking Resources Clocking Option Slave ClockingTSClk Clocking Resources Clocking Option Instantiating Multiple Cores Multiple Core ImplementationsCreating Top-Level UCF File Generating the CoresMultiple Core Implementations Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Generating a Simulation Model with Initialized Calendar Simulating and Implementing the CoreFunctional Simulation Generating a Simulation ModelSimulating and Implementing the Core Timing SimulationSynthesis SynthesisSynthesis of Example Design SynplifyMapping the Design Xilinx Tool FlowExample Design Script NGDBuildGenerating a Bitstream Static Timing AnalysisXilinx Tool Flow 130 Eops SPI-4.2 Lite Control WordDIP-4 Example SPI-4.2 Lite Calendar ProgrammingAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification