R

Chapter 2: Core Architecture

Source Status and Flow Control Interface (Calendar Control and Status FIFO)

The Source Status and Flow Control Interface enables you to receive flow control data from the SPI-4.2 interface. The status information is received based on the channel order and frequency defined in the programmable calendar. The Source Calendar Control signals are defined in Table 2-13. The Source Status FIFO Signals are defined in Table 2-14. Table 2-15defines Source Static Configuration signals.

Table 2-13:Source Calendar Control Signals

Name

 

Direction

 

Clock

Description

 

 

Domain

 

 

 

 

 

 

 

 

 

 

 

SrcCalClk

 

Input

 

n/a

Source Calendar Clock: All Source calendar signals are synchronous

 

 

 

 

 

to this clock.

 

 

 

 

 

 

SrcCalWrEn_n

 

Input

 

SrcCalClk

Source Calendar Write Enable: When this signal is asserted (Active

 

 

 

 

 

Low), the Source Calendar is loaded with the data on the SrcCalData

 

 

 

 

 

bus on the rising edge of SrcCalClk.

 

 

 

 

 

 

SrcCalAddr[8:0]

 

Input

 

SrcCalClk

Source Calendar Address: When SrcCalWrEn_n is asserted, this bus

 

 

 

 

 

indicates the calendar address to which the data on SrcCalData is

 

 

 

 

 

written. When SrcCalWrEn_n is deasserted, this bus indicates the

 

 

 

 

 

calendar address from which the data on SrcCalDataOut is driven.

 

 

 

 

 

 

SrcCalData[7:0]

 

Input

 

SrcCalClk

Source Calendar Data: This bus contains the channel number to

 

 

 

 

 

write into the calendar buffer when SrcCalWrEn_n is enabled. The

 

 

 

 

 

channel numbers written into the calendar indicate the order that

 

 

 

 

 

status is updated on the SrcStat bus.

 

 

 

 

 

 

SrcCalDataOut[7:0]

 

Output

 

SrcCalClk

Source Calendar Data Output: This Source Calendar Data Output

 

 

 

 

 

bus contains the channel number that is read from the calendar buffer

 

 

 

 

 

when SrcCalWrEn_n is disabled. The channel numbers read from the

 

 

 

 

 

calendar indicates the order that status is updated on SrcStat bus.

 

 

 

 

 

 

Table 2-14:Source Status FIFO Signals

 

 

 

 

 

 

 

Name

 

Direction

 

Clock

Description

 

 

Domain

 

 

 

 

 

 

 

 

 

 

 

SrcStatClk

 

Input

 

n/a

Source Status Clock: For the Addressable Interface, all Source Status

(Addressable I/F

 

 

 

 

read signals are synchronous to this clock.

 

 

 

 

 

Only)

 

 

 

 

For the Transparent Interface, this clock signal is not present. For this

 

 

 

 

 

interface, all signals are synchronous to TSClk_GP.

 

 

 

 

 

 

SrcStat[31:0]

 

Output

 

SrcStatClk

Source Status: For the Addressable Interface, the 32-bit Source Status

(Addressable I/F

 

 

 

(Addressabl

bus is the dedicated 16-channel interface. You can read the status for

 

 

 

16-channels each clock cycle. The 16-channel status that are accessed

Only)

 

 

 

e I/F only)

 

 

 

simultaneously are grouped in the following manner: channel 15 to

 

 

 

 

 

 

 

 

 

TSClk_GP

0, channel 31 to 16, channel 47 to 32, ..., channel 255 to 240.

 

 

 

 

For the Transparent Interface, this Source Status bus is two bits wide

SrcStat[1:0]

 

 

 

(Transparent

 

 

 

and represents the last status received.

(Transparent I/F Only)

 

 

 

I/F only)

 

 

 

 

 

 

 

 

 

 

 

 

36

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UG181 June 27, 2008

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Xilinx UG181 manual Source Status Fifo Signals
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UG181 specifications

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