Xilinx UG181 manual Reset, Hunt, Sync Wait

Sink Core

R

Figure 4-15shows a state machine diagram illustrating the Sink core startup sequence and error condition processing.

Consecutive DIP4	FIFO Reset
Errors Received;
	Asserted
Almost Full and
	Data Transition Detected
FifoAFMode = "00"

Reset De-asserted;

Sink Enabled

RESET	HUNT	SYNC	SYNC	SYNC
		WAIT	DATA	TRAIN

Training Pattern

Reset Asserted; Sink Disabled

Detected

Consecutive Valid	Valid SOP to Data
	Transition Detected;
Training Sequences
	FIFO Reset De-asserted
Received

Figure 4-15:Sink Startup Sequence State Machine

Reset

The Sink core remains in the Reset state until the following conditions are true:

•Reset_n is deasserted

•SnkEn is asserted

In this state, the Sink core transmits framing patterns (11) on RStat[1:0]. The core is Out of Frame in this state.

Hunt

The core remains in the hunt state until a set number of consecutive training patterns are received as defined by the parameter NumTrainSequences

In this state, the Sink core transmits framing patterns (11) on RStat[1:0]. The core is Out of Frame in this state.

Sync Wait

In the Sync Wait state, the Sink core has completed the start-up sequence and is waiting to receive the first valid SOP to data transition on RDat.

The Sink core will remain in this state until the following conditions are true:

•SnkFifoReset_n is deasserted

•The first valid SOP-to-data transition is received on RDat

In this state, the Sink core continuously checks DIP-4 parity, and sends FIFO Channel status on RStat. The core is In Frame in this state.

SPI-4.2 Lite v4.3 User Guide www.xilinx.com 71

UG181 June 27, 2008