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Xilinx UG181 manual Slave Clocking, 3SysClk Clocking Resources Clocking Option

Models: UG181

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Source Clocking Options

R

The clock implementation for SysClk and TSClk is selected in the CORE Generator GUI. Depending on the chosen clocking option, different clock resources will be used. Table 6-3and Table 6-4provide the clocking resource count for each clocking option.

Table 6-3:SysClk Clocking Resources

Clocking Option	BUFR	BUFG	DCM

Global Clocking	0	1	1

Regional Clocking	1	0	0

Table 6-4:TSClk Clocking Resources

Clocking Option	BUFR	BUFG	DCM

Global Clocking	0	1	0

Regional Clocking	1	0	0

Slave Clocking

The Source slave clocking configuration allows users to fully customize the way the Source core clocks are implemented. When implementing multiple SPI-4.2 Lite cores in a single device, the user can have one master clocking SPI-4.2 Lite core which provides the clocking for all Source slave clocking cores. The user can also implement a single slave-clocking module that can be used to drive the clocks for all Source cores. An example file is provided (pl4_lite_src_clk.v/.vhd) to demonstrate how to implement a clocking module for the Source core. An illustration of the Slave clock inputs and this example module are shown in Figure 6-10and the inputs are defined in Table 2-18, page 41.

SysClk_P

SysClk_N

TSClk

Slave

Clocking

Example Module

SPI-4.2 Lite Source Core

(Configured with Slave Clocking)

	SysClk0_buf			SysClk0_GBSLV
	SysClk0_buf

	SysClk180_buf
	SysClk180_buf
				SysClk180_GBSLV
	TSClk_buf			SysClk180_GBSLV
	TSClk_buf			TSClk_GBSLV
				TSClk_GBSLV

Figure 6-10:Slave Clocking Inputs

The clocking implementation in the example file provided (pl4_lite_src_clk.v/.vhd) is customized based on the user selected parameters in the Coregen GUI. The global or regional selections for SysClk and TSClk will be reflected in this slave clocking example file. The implementations of global and regional clocking provided in the example file are identical to the internal implementations described in the master clocking section.

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual Slave Clocking, 3SysClk Clocking Resources Clocking Option, TSClk Clocking Resources Clocking Option

Contents

UG181 June 27 LogiCORE IP SPI-4.2 LiteDate Version Revision SPI-4.2 Lite v4.3 User Guide UG181 June 27Table of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide 1SPI-4.2 Lite Core in a Typical Link Layer Application Schedule of Figures30Addressable Status Fifo Interface 4-Channel Configuration Generating the Core Designing with the Core Schedule of TablesAppendix a SPI-4.2 Lite Control Word About This Guide ContentsTypographical ConventionsConventions Online DocumentPreface About This Guide Additional Core Resources IntroductionAbout the Core Recommended Design ExperienceDocument Technical SupportFeedback SPI-4.2 Lite CoreSystem Overview Core ArchitectureCore Architecture Sink CoreSource Core Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram RCtlN Sink SPI-4.2 InterfaceSink Control and Status Interface Sink User InterfaceSink Fifo Interface 3Sink Fifo Signals NameCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate RDClk0 General Purpose Sink Clocking InterfaceRDClk0USER This clock Source Core InterfacesSource Core Interfaces Source SPI-4.2 InterfaceDomain Source User InterfaceSource Control and Status Interface 16 bytes with no EOP Name Direction Clock Description Domain Source Fifo Interface14 Source Status Fifo Signals Source Status Address Source Static Configuration InterfaceSource Almost Full Threshold Assert Source Calendar Period The SrcCalendarM Source Clocking InterfaceSysClk0 General Purpose Domain Core Architecture Core Generator Graphical User Interface Generating the CoreCore Options Main ScreenSink Status Options Screen Component NameStatus Interface CalendarFlow Control Fifo Threshold Sink Other Options ScreenSynchronization Clock Distribution Clock ModeSource Status Options Screen ClockingBursting Source Other Options ScreenTSClk Distribution Burst ModeBurst Size in Credits SysClk DistributionCalendar COE File Format Know the Degree of Difficulty Understand Signal PipeliningDesigning with the Core General Design GuidelinesUse Supported Design Flows Recognize Timing Critical SignalsInitializing the SPI-4.2 Lite Core Keep it RegisteredSink Data Path Example Sink CoreBasic Operation SPI-4.2 Interface1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP Sink Fifo RCtlSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Almost Empty Sink Fifo Interface SignalsSink Almost Full Sink Fifo EmptySink Overflow Sink Status and Flow Control SignalsInitializing the Calendar In-Circuit Sink Calendar Initialization7Sink Calendar Initialization Sink Flow Control8Typical Flow Control Implementation for 4-Channel System 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3 Sink Status Fifo Interface ExampleSink Status Fifo Status Interface Example FifoAFMode and Sink Almost Full Sink Static Configuration SignalsInsertion of DIP2 Errors Fifo Almost Full Mode12FIFO Almost Full Mode DCM Alignment Implementation Considerations Fifo Almost Full Mode 10 orSink Data Capture Implementation Static AlignmentSynchronization and Start-up Sync Wait ResetHunt In-Frame and Out-of-Frame Behavior Error HandlingSync Data Sync TrainLoss of RDClk Sink Fifo Burst ErrorSink SPI-4.2 Bus Error and Sink Bus Error Status70 EOP Abort HandlingSequential End-of-Burst Control Words Sink DIP-4 Error HandlingSequential Payload Control Words 18Example of Error Flag SnkFFDIP4Err Reserved Control Words Source CoreSource Core Source Data Path Example22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Transmitting Idle Cycles Inserting DIP4 ErrorsSource Control and Status Signals Source Fifo Almost Full Source Fifo Interface Signals24Source Fifo Almost-full Condition Source Fifo OverflowWriting to the Source Fifo Source Status and Flow Control SignalsInsertion of DIP-4 Errors 27Typical User Design Example Source Calendar Initialization28Source Calendar Initialization Source Flow Control Addressable Status Interface29Addressable Status Fifo Interface Addressable Status Fifo Interface Example30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Burst Mode Source Static Configuration Signals35Example Of Source Burst Mode = Source Burst Mode ExampleReset Source Out of Frame Source Behavior Before SynchronizationSource Behavior After Synchronization EOP Abort InsertionIncorrect Burst Termination Source DIP-2 Error HandlingSource Pattern Error Handling Source Status Frame Word HandlingDesigning with the Core Timing Constraints Constraining the CoreOverview Sink Core Required ConstraintsConstraining the Core Maxdelay for ResetTime Names for Clocks Timespecs for ClocksSink Core Required Constraints Phase Shift for DCMClock Delay in Iserdes DCM and Static Alignment ConstraintsPlacement Placement ConstraintsIOB Register Packing IDelayCtrlSink Core Optional Constraints Standards ConstraintsTimenames for Clocks Source Core Required ConstraintsArea Group Constraints Timing Ignore ConstraintsSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsNew Target Region or Device Package User ConstraintsConstraints Migration Source Core Modifying the UCF FileTarget Device Sink CoreInst TSClk LOC = Bank3 Embedded Clocking Special Design ConsiderationsSink Clocking Options Special Design Considerations User Clocking2Sink Core User Clocking Resources Clocking Option Global ClockingSink Clocking Options 3Sink User Clocking Global Clocking Regional ClockingSource Clocking Options Source Clocking Options5Source Clocking Master and Slave Implementation Master ClockingIOB 8Source Clocking Regional Clocking for SysClk TSClk Clocking Resources Clocking Option Slave Clocking3SysClk Clocking Resources Clocking Option Instantiating Multiple Cores Multiple Core ImplementationsMultiple Core Implementations Generating the CoresCreating Top-Level UCF File Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Generating a Simulation Model with Initialized Calendar Simulating and Implementing the CoreFunctional Simulation Generating a Simulation ModelSimulating and Implementing the Core Timing SimulationSynthesis SynthesisSynthesis of Example Design SynplifyMapping the Design Xilinx Tool FlowExample Design Script NGDBuildXilinx Tool Flow Static Timing AnalysisGenerating a Bitstream 130 Eops SPI-4.2 Lite Control WordDIP-4 Example SPI-4.2 Lite Calendar ProgrammingAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification