Sink Core

R

SnkCalAddr=1, and so forth, until the end of the Calendar is reached, as defined by

SnkCalendar_Len.

The waveform in Figure 4-7illustrates the programming of the Sink Calendar. In this example, SnkCalendar_Len is set to five and SnkCalendar_M is set to zero; indicating that the calendar length is six, and should be repeated once. This means that the Sink Calendar will be expected to drive the FIFO Status Channel data (onto the SPI-4.2 bus) in the following sequence: status for channel 3, status for channel 0, status for channel 1, status for channel 2, status for channel 3, and status for channel 0.

To verify what is programmed into the calendar buffer, read the contents using the Sink Calendar Data Out bus SnkCalDataOut[7:0]. When the calendar write enable signal is deasserted, the data stored in the location specified by the calendar address is driven onto the SnkCalDataOut bus.

Note: For a 1-channel system, it is not necessary to program the Calendar since, by default, all locations are set to zero.

SnkCalendar_M

 

 

SnkCalendar_M=0 (0000.0000)

 

 

 

SnkCalendar_Len

 

 

SnkCalendar_Len=5 (0.0000.0101)

 

 

 

SnkCalClk

 

 

 

 

 

 

 

 

SnkCalWrEn_n

 

 

 

 

 

 

 

 

SnkCalAddr[8:0]

0x00

0x01

0x02

0x03

0x04

0x05

0x00

0x01

SnkCalData[7:0]

CH3

CH0

CH1

CH2

CH3

CH0

 

 

SnkCalDataOut[7:0]

 

 

 

 

 

 

 

CH3

Figure 4-7:Sink Calendar Initialization

Sink Flow Control

Typically, there are two ways to implement the SPI-4.2 Lite Sink flow control:

Automatic: For a single channel system or a system that does not require flow control on a per-channel basis, the SPI4.2 Lite Sink core can be configured to perform flow control automatically. See “FifoAFMode and Sink Almost Full,” page 67.

Manual: When per-channel flow control is required, the interface is fully customizable. A typical implementation is shown in Figure 4-8. In this case, external FIFOs are used to provide additional per-channel storage and to facilitate per-channel flow control. A programmable full indication on the individual user FIFOs can be used to drive the status interface of the Sink core. This provides flexibility in implementing the optimal flow control to meet individual system requirements.

If implementing large channel solutions, the individual user FIFOs may be shared by sets of channels or alternative approaches may be implemented that enable minimizing the external logic required.

The Sink Status FIFO interface has a 32-bit bus for all channel configurations (e.g., whether the core is configured for four channels or 128 channels or 256 channels). This allows you to write the FIFO Status Channel data for 16 channels at a time. There are four address lines for selecting which 16 channels to access. (For systems using 1-16 channels, the address lines can be permanently set to zero.) The latency between the user interface and SPI-4.2 Interface for the Sink Status Path is seven RSClk cycles and one SnkStatClk cycle.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

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UG181 June 27, 2008

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Xilinx UG181 manual Sink Flow Control, 7Sink Calendar Initialization

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.