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Chapter 4: Designing with the Core

setting has the added advantage of providing a benchmark of the system margin, based on the UI (unit interval or bit time).

System Margin (ps) = UI(ps) * (working phase shift range/128)

Xilinx does not recommend that a single DCM PHASE_SHIFT value will be effective across all hardware platforms. Xilinx also does not recommend that you attempt to determine the PHASE_SHIFT setting empirically. In addition to the clock-to-data phase relationship, other factors such as package flight time (package skew) and clock routing delays (internal to the device) affect the clock-data relationship at the sample point (in the IOB) and are difficult to characterize.

The optimal PHASE_SHIFT setting should be investigated during hardware integration and debugging. Note that the phase shift setting provided with the SPI-4.2 Lite core in the constraints file is only a place holder. This default setting has changed over various SPI-4.2 Lite releases to account for changes to the DCM DESKEW ADJUST attribute. For further information on how to find the ideal phase shift value for your system, see the Xilinx SPI-

4.2solution record 16112.

Note: This alignment method can be used only with global clock distribution.

ISERDES Alignment Implementation Considerations (Virtex-4 and Virtex-5 only)

Static alignment can be performed using the IDELAY function of the Virtex-4 and Virtex-5 device ISERDES for regional clocking distribution. The ability of the IDELAY function to delay its input by small increments (75ps), enables the internal RDClk to be shifted relative to the sampled data. For statically aligned systems, the delay chain length is a critical path of the system. The static alignment solution assumes that the PCB is designed with precise delay and impedance matching for all LVDS differential pairs of the data bus. In this case, the primary alignment mechanism is time shifting the internal RDClk relative to the data bits using the IDELAY function.

you must determine the optimal delay in the ISERDES (IOBDELAY) to ensure that the target system will have the maximum system margin and performance across voltage, temperature, and process (chip to chip) variations. Xilinx does not recommend a single IOBDELAY value that will be effective across all hardware platforms. Xilinx also does not recommend that you attempt to determine the IOBDELAY setting empirically. In addition to the clock-to-data phase relationship, other factors such as package flight time (package skew) and clock routing delays (internal to the device) affect the clock data relationship at the sample point (in the IOB) and are difficult to characterize. The optimal IOBDELAY setting should be investigated during hardware integration and debugging. Note that the IOBDELAY setting provided with the SPI-4.2 Lite core in the constraints file is only a place holder.

An example of this implementation is available through the GUI using the Sink core in user clocking mode with regional clocking distribution.

Synchronization and Start-up

After the sink core has been initialized, as described in the “Initializing the SPI-4.2 Lite Core,” it has to be synchronized before data and status can be received and transmitted.

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UG181 June 27, 2008

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Xilinx UG181 manual Synchronization and Start-up
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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