Source Other Options Screen

R

Burst Size in Credits

This is the value of static configuration signal SrcBurstLen; it is the maximum burst length in credits. The valid range is from 1 to 63.

Burst Mode

This is the value of static configuration signal SrcBurstMode. It specifies how the Source core transmits data. Complete Bursts Only causes the core to send only data bursts that are of Burst Size (as defined above) or terminated by an EOP. Segmentation of Bursts at Credit Boundary causes the core to send data bursts that terminate at any credit boundary or with an EOP. See“Source Burst Mode,” page 93.

FIFO Threshold

This option lets you select the default static configuration parameters for Source core FIFO Threshold behavior.

Almost Full Assert

This is the value of static configuration signal SrcAFThresAssert; it is the internal FIFO level at which the Source core will assert SrcFFAlmostFull_n. When the burst mode is selected to be complete burst only, the valid range of SrcAFThresAssert is from SrcBurstLen to 508, otherwise the valid range is from 6 to 508. The Almost Full Assert value is measured from the full level. For example, if the value chosen is 40, SrcFFAlmostFull_n will be asserted when there are 40 FIFO locations empty.

Almost Full Negate

This is the value of static configuration signal SrcAFThresNegate; it is the internal FIFO level at which the Source core will deassert SrcFFAlmostFull_n. The valid range is the Almost Full Assert value to 508 and is also measured from the full level.

Clocking

Clock Mode

The Source core netlist will contain a complete clocking solution if Master Clocking is selected. If Slave Clocking is selected, you must provide a clock generation method external to the Source core. For more information, see “Source Clocking Options,” page 115.

SysClk Distribution

For Virtex-4 and Virtex-5 FPGA designs, the SysClk internal clocking implementation uses either the global clock buffers or the regional clock buffers. For more information, see “Source Clocking Options,” page 115.

TSClk Distribution

For Virtex-4 FPGA designs, the TSClk internal clocking implementation uses either the global clock buffers or the regional clock buffers. For more information, see “Source Clocking Options,” page 115.

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UG181 June 27, 2008

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Xilinx UG181 manual Burst Size in Credits, Burst Mode, SysClk Distribution, TSClk Distribution, Source Other Options Screen
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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