Sink Core

R

♦SnkBusErrStat[5]: Control word with payload bit not set and non-zero address (excluding Training Control word).

♦SnkBusErrStat[7:6]: Tied to zero. (reserved)

If the core receives two (or more) back-to-back payload control words, the last one received is used and the others are discarded. If the core receives two (or more) EOPs back-to-back, the first one is used and the others are discarded. For more information see “Error Handling,” page 72.

•Sink Bus Error (SnkBusErr) is asserted active high when any of the error conditions that flags the Sink Bus Error Status bus is triggered. SnkBusErr is triggered concurrently with SnkBusErrStat.

For each SPI-4.2 protocol violation or error that triggers SnkBusErr or SnkBurErrStat, these signals will be asserted for at least one RDClk0_GP clock cycle translated into the SnkFFClk domain.

•Sink Training is Valid (SnkTrainValid) is asserted when valid training data is received. The behavior of this signal is illustrated in the timing diagram in Figure 4-3. As is shown, the SnkTrainValid signal is driven high for the duration of a complete training pattern after it has successfully been received.

Idle

Training Control

Training Data

Multiple Training

Training Data

Patterns

 

 

 

 

RdClk

 

 

 

 

RDat 000F

0FFF

F000

0FFF

F000

SnkFFClk

SnkTrainValid

Figure 4-3:Sink Training Valid Status

•SnkFifoReset_n is used when you want to clear the FIFO (and the associated data path logic) while remaining in frame. When SnkFifoReset_n is deasserted, the Sink data path will not write data into the FIFO until a packet with a valid SOP is received.

•Reset_n is used when you want to restart the entire Sink core. It will cause the interface to go out-of-frame. When Reset_n is deasserted, the Sink core will initiate the synchronization start-up sequence.

Sink FIFO Interface Signals

The Sink FIFO Interface signals allow you to access the data (received on the SPI-4.2 Interface) that is stored in the FIFO. These signals are defined in Table 2-3. Waveforms illustrating the handshaking and FIFO status signals are shown in Figure 4-4and Figure 4-5. The Sink FIFO Interface signals are synchronous to SnkFFClk, and the FIFO is 510 words deep. A FIFO word is 1/2 credit wide for the 64-bit interface, and 1/4 credit wide for the 32-bit interface.

Sink FIFO Almost Empty

The behavior of the Almost Empty (SnkFFAlmostEmpty_n) status signal is illustrated in Figure 4-4. As is shown in this waveform, the Almost Empty flag is asserted with the second to last word read out of the FIFO. When this signal is asserted (active low), it indicates that one word remains in the FIFO, and the read enable signal should be

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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

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In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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