R

Chapter 2: Core Architecture

Table 2-5:Sink Status FIFO Signals (Continued)

Name

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

SnkStatAddr[3:0]

Input

SnkStatClk

Sink Status Address bus: The Sink Status Address determines the

 

 

 

group of 16-channel status that SnkStat will be updating.

 

 

 

Bank 0: SnkStatAddr=0, channels 15 to 0

 

 

 

Bank 1: SnkStatAddr=1, channels 31 to 16

 

 

 

Bank 2: SnkStatAddr=2, channels 47 to 32

 

 

 

. . .

 

 

 

Bank 15: SnkStatAddr=15, channels 255 to 239

 

 

 

 

SnkStatWr_n

Input

SnkStatClk

Sink Status Write: The Sink Status Write (active low) qualifies the

 

 

 

SnkStatMask signal. When SnkStatWr_n is asserted (active low),

 

 

 

status for the different channels is updated. When SnkStatWr_n is

 

 

 

deasserted (active high), SnkStat input is ignored.

 

 

 

 

SnkStatMask[15:0]

Input

SnkStatClk

Sink Status Mask Bus: The Sink Status Mask determines if the 2-bit

 

 

 

status among the corresponding group of 16 channels of status on

 

 

 

SnkStat (being addressed by SnkStatAddr) will be updated when

 

 

 

SnkStatWr_n is asserted (active low):

 

 

 

SnkStatMask[x] = 1, status for channel (x+(SnkStatAddr*16)) will be

 

 

 

updated.

 

 

 

SnkStatMask[y] = 0, status for channel (y+(SnkStatAddr*16)) will not

 

 

 

be updated.

 

 

 

For example, if SnkStatMask[15] = 1 and SnkStatAddr = 1, then

 

 

 

SnkStat[31:30] = 00 will overwrite the current status on channel 31. If

 

 

 

SnkStatMask is all zeros, none of the sixteen 2-bit status values will

 

 

 

be updated. If SnkStatMask is all ones, all sixteen of the 2-bit status

 

 

 

values will be updated.

 

 

 

 

Sink Static Configuration Interface

These signals are inputs to the core that are statically driven by setting them to a constant value in the top-level wrapper file. The SPI-4.2 Lite release includes a wrapper file that has the static configuration signals connected to the values selected in the CORE Generator GUI. Customization of these signals can be done using the GUI.

Two of the Sink Static Configuration signals can be changed in circuit. There are static registers for SnkCalendar_M and SnkCalendar_Len that are synchronous to SnkStatClk. To change these parameters while the core is operational, SnkEn must first be deasserted.

If you sets the configuration signal to an illegal number, the core is automatically set to the minimum value. Table 2-6defines the Sink Static Configuration signals.

26

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

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Xilinx UG181 manual Sink Static Configuration Interface
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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