Source Core

R

Action: The Source core will transmit idle cycles when Reset_n is asserted. When Reset_n is deasserted, the core will initiate the synchronization start-up sequence.

Case 2: If the core receives a number of consecutive DIP-2 errors as defined by

NumDip2Errors.

Action: The Source core terminates the current packet at the next burst boundary, and begins transmitting training patterns on TDat[15:0].

Case 3: If the core receives four framing sequences "11" in a row on TStat.

Action: The Source core terminates the current packet at the next burst boundary, and begins transmitting training patterns on TDat[15:0].

After the Source core is in frame, it will resume transmitting the remaining data stored in the FIFO. (Note that if SrcFifoReset_n is asserted, the Source core will remain in frame (SrcOof will be deasserted).

Source DIP-2 Error Handling

The Source core asserts the DIP-2 error flag (SrcDIP2Err) when a DIP-2 error is received on TStat.

Source Status Frame Word Handling

The Source core asserts the frame error flag (SrcStartFrameErr) when an incorrect frame word (non-”11”) is received on TStat at the end of the status sequence.

Source Pattern Error Handling

Source Pattern Error (SrcPatternErr) is asserted when an illegal data pattern is written into the Source FIFO. The two conditions that will trigger this error signal are:

Case 1: The address was changed on a non-credit boundary, without an EOP: In this case, the remainder of that packet will be terminated with an EOP Abort, and sent out the SPI-4.2 bus.

Case 2: The SrcFFMod signal is non-zero without an EOP: In this case, an EOP abort will not be asserted. When this occurs, the Source core will ignore the SrcFFMod value and send the data word with MOD set to zero.

Incorrect Burst Termination

When a burst (that has an odd number of bytes), terminated with an EOP, is not padded with zeros, the Source core sets unused bytes to zero (as required by the SPI4 specification). The Source core will also assert SrcPatternErr, but the core will not assert an EOP abort.

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UG181 June 27, 2008

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Xilinx UG181 manual Source DIP-2 Error Handling, Source Status Frame Word Handling, Source Pattern Error Handling

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.