Sink Status Options Screen

R

Calendar

Options in this section affect the behavior of the Sink core with respect to its calendar and status interfaces.

Iterations of Calendar Sequence Before DIP2

This is the value of static configuration signal SnkCalendar_M; it is the number of times the Sink core will repeat the calendar sequence before sending a DIP2 value and frame word on RStat. The valid range is 1 to 256.

Length of Calendar Sequence

This is the value of static configuration signal SnkCalendar_Len; it is the number of entries in the calendar sequence. The valid range is 1 to 512.

Load Init File

If this option is selected, the Sink core calendar block RAM will be initialized at startup with a sequence loaded from a COE file. The sequence can be overwritten at runtime via the calendar interface.

Load Coefficients

For this option, select the name of the COE file with the calendar programming information. For more information see “Calendar COE File Format,” page 50.

Show Coefficients

This shows the contents of the loaded COE file.

Flow Control

This option selects the value of static configuration signal FifoAFMode; it determines the behavior of the Sink core status interface when the internal FIFO is almost full. See “FifoAFMode and Sink Almost Full,” page 67.

Send Satisfied on All Channels

This causes the Sink core to send the satisfied (“10”) status on RStat for each channel.

Send Framing

This causes the Sink core to send framing (“11”) on RStat and go out-of-frame.

Send Current Status

This causes the Sink core to continue sending the stored status value on RStat for each channel.

Status Interface

This option selects the default static configuration parameters for Sink core status channel clocking and I/O type.

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UG181 June 27, 2008

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Xilinx UG181 manual Calendar, Flow Control, Status Interface

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.