R

Appendix C

SPI-4.2 Lite Core Verification

Extensive software testing with an internally developed test suite is performed for each SPI-4.2 Lite release. Using our in-house verification environment, the SPI-4.2 Lite Core was tested in RTL, post-ngdbuild, and timing simulation. When using the in-house verification environment, the SPI-4.2 Lite core was tested in three stages:

•Functional (RTL) verification

•Gate-level (post ngdbuild back-annotation HDL) verification

•Gate-level with back-annotated timing (with SDF file) verification targeting the following device/frequency combinations:

-Virtex-5 devices up to 550 Mbps on the SPI-4.2 interface and 275 MHz on the user interface (SrcFFClk and SnkFFClk)clocks.

-Virtex-II devices up to 320 Mbps on the SP1-4.2 interface and 160 MHz on the user interface (SrcFFclk and SnkFFClk) clocks

-Virtex-II Pro devices up to 320 Mbps on the SP1-4.2 interface and 160 MHz on the user interface (SrcFFClk and SnkFFClk) clocks

-Virtex-4 devices up to 380 Mbps on the SP1-4.2 interface and 190 MHz on the user interface (SrcFFClk and SnkFFClk) clocks

-Spartan™-3 devices up to 230 Mbps on the SP1-4.2 interface and 115 MHz on the user interface (SrcFFClk and SnkFFClk) clocks

-Spartan-3A/3AN/3A DSP devices up to 210 Mbps on the SPR-4.2 interface and 105 MHz on the user interface (SrcFFClk and SnkFFClk) clocks

-Spartan-3E devices up to 180 Mbps on the SP1-4.2 interface and 90 MHz on the user interface (SrcFFClk and SnkFFClk) clocks

For each of these stages, each feature of the SPI-4.2 Lite core was fully verified. The following are examples of stimulus used to verify the features:

•Verification of valid data:

♦SPI-4.2 bus traffic that contains short packets that were smaller than one credit (16 bytes)

♦SPI-4.2 bus traffic that contains long packets that were larger than one credit (16 bytes)

♦SPI-4.2 bus traffic of a constant packet size

♦SPI-4.2 bus traffic of a variable packet size

♦SPI-4.2 bus traffic that consisted of a single burst or packet

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual SPI-4.2 Lite Core Verification
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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