Source Core

R

Writing to the Source FIFO

A pause to a transfer on a credit (16 bytes) boundary is illustrated in Figure 4-26. In the example shown, two packets for unique channels are transferred into the FIFO. You write 32 bytes of data for channel 1, followed by 32 bytes of data for channel 2. Next, the final eight bytes of data and associated EOP for channel 1 is written to the FIFO. Finally, the remaining 16 bytes of data and associated EOP is written into the FIFO for channel 2. The data will be transferred across the SPI-4.2 bus in the same order it is written into the FIFO

SrcFFClk

SrcFFWrEn_n

SrcFFAddr

CH1

CH2

CH1

CH2

SrcFFData

 

 

 

 

SrcFFMod

000

000

 

000

SrcFFSOP

SrcFFEOP

SrcFFErr

SrcFFAlmostFull_n

SrcFFOverflow_n

Figure 4-26:Writing to the Source FIFO

Insertion of DIP-4 Errors

The Source core enables you to force the insertion of DIP4 error for use during system testing and debugging. This is supported by the SrcFFErr signal. When a SrcFFEOP flag is asserted, SrcFFErr is used to indicate that the current packet contains an error and causes the core to transmit an EOP abort with the packet. When SrcFFEOP is not asserted, the assertion of SrcFFErr causes the core to force the insertion of an EOP (1 byte or 2 bytes depending on SrcFFMod) with an erroneous DIP4 value when this data is transmitted on the TDat bus. The erroneous DIP4 value is an inversion of the correctly calculated DIP4 value. Note that the DIP-4 error insertions are independent of SrcFFSOP.

Source Status and Flow Control Signals

The Source core transmits data in the order that it was written to the FIFO. You can pause data transmission by sending idle cycles (using IdleRequest) or training (TrainingRequest), but unless the FIFO is cleared (Reset_n or SrcFifoReset_n), the data written into the FIFO will be transmitted in order. Ensure that proper data scheduling is implemented to prevent a channel from going hungry or overflowing. This can be accomplished using the status information from the Source core to determine which channel data should be written next. A typical user flow-control design is shown in Figure 4-27. This is an illustration of a two-channel system. The diagram shows an arbiter that is used to poll the FIFO Status for each channel. It then uses this information to determine which data is written to the Source core FIFO.

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UG181 June 27, 2008

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Xilinx UG181 manual Source Status and Flow Control Signals, Writing to the Source Fifo, Insertion of DIP-4 Errors
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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