Xilinx UG181 manual Regional Clocking, 3Sink User Clocking Global Clocking

R

Chapter 6: Special Design Considerations

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BUFG

RDClk0_USER

100 MHz

RDClk180_USER

CLK0 DCM

CLK180

CLK2X

IBUFGDS

RDClk

100 MHz

IOB

DCMReset_RDClk

Locked_RDClk

Denotes I/O on User Interface

100 MHz Path

IOB DDR Flops

Sink Internal

Data & Control

Bus

Q D

16

32

RDClk0_GP16

100 MHz

200 MHz Path

QD

Q D

RDat[15:0] & RCtl

RDClk0_GP

100 MHz

RDClk180_GP 100 MHz

IOB

	Internal Bus		D		Q	RStat[1:0] & RSClk
RStat[1:0] & RSClk						25 MHz
		RDClk0_GP
		100 MHz		EN
	Enable at ¼ (or 1/8) PL4 Rx data rate

Figure 6-3:Sink User Clocking: Global Clocking

IOB

Regional Clocking

This implementation uses the regional clock buffer resources BUFIO and BUFR to generate

afull-rate clock (RClk0_USER) and inverted full-rate clock (RDClk180_USER). The user clocking module also contains IDELAYCTRL and IDELAY modules for phase-shifting the clock outputs. This is a requirement for static alignment of the clock to the data eye.

Regional clocking distribution in the Sink core requires a 200 MHz reference clock to clock the IDELAYCTRL module. This guarantees predictable tap delays when shifting the clocks with the IDELAY module. This extra clock should be considered when implementing regional clocking in the Sink core. The regional clocking configuration is illustrated in Figure 6-4. Note that the inverter used to generate the RDClk180_USER clock will be absorbed into the DDR flops.

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		UG181 June 27, 2008