Xilinx UG181 DCM and Static Alignment Constraints, Phase Shift for DCM, Clock Delay in Iserdes

Models: UG181

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Sink Core Required Constraints

R

NET

"<snk_instance_name>/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/rs clk_rst" MAXDELAY = 5.8 ns;

NET

"<snk_instance_name>/U0/pl4_lite_snk_reset01/snk_stat_clk_gen/ reset_out_i" MAXDELAY = 5.8 ns;

NET

"<snk_instance_name>/U0/pl4_lite_snk_reset01/snk_ff_clk_rst_gen /reset_out_i” MAXDELAY = 5.8 ns

NET

"<snk_instance_name>/U0/pl4_lite_snk_reset01/snk_ff_clk_rst_gen /fifo_reset_out_i" MAXDELAY = 5.8 ns;

NET

"<snk_instance_name>/U0/pl4_lite_snk_reset01/rdclk0_rst_gen/ fifo_reset_out_i” MAXDELAY = 5.8 ns;

NET

"<snk_instance_name>/U0/pl4_lite_snk_reset01/rdclk0_rst_gen/ reset_out_i" MAXDELAY = 5.8 ns;

These MAXDELAY values differ depending on target speed grade and core performance.

DCM and Static Alignment Constraints

DCM and BUFR (Virtex-4 and Virtex-5 devices only) constraints are needed to align incoming data (RDat and RCtl) to its clock (RDClk) in the static alignment configuration. In addition, the frequency of the DCM clock input must also be specified for complete timing analysis. The following constraints are provided with the SPI-4.2 Lite core. You can modify these constraints to meet your system requirements.

Phase Shift for DCM

The following constraints are used to align the incoming data (RDat and RCtl) to its clock (RDClk) when global clocking is used. This is accomplished by changing the phase of the I/O clock in relation to the data. The default PHASE_SHIFT value of 62 is the correct nominal “PHASE_SHIFT,” assuming RDClk transitions at the same time as RDat and RCtl inputs.

INST "<snk_instance_name>/U0/pl4_lite_snk_clk0/rdclk_dcm0"

CLKOUT_PHASE_SHIFT = FIXED;

INST "<snk_instance_name>/U0/pl4_lite_snk_clk0/rdclk_dcm0" PHASE_SHIFT = 62;

Clock Delay in ISERDES

The following constraint applies to Virtex-4 and Virtex-5 devices only, and is needed to align the incoming data (RDat and RCtl) to its clock (RDClk) at the ISERDES. The alignment method can be used only when sink user clocking mode with regional clocking distribution is selected. Alignment is accomplished by delaying the RDClk input in the ISERDES using the “IOBDELAY” attribute. The default value in the UCF is the correct “IOBDELAY” for the defined RDClk frequency, assuming RDClk transitions at the same time as RDat and RCtl inputs. Each increment or decrement of the IOBDELAY value shifts the RDat and RCtl input by 75 ps forwards or backwards. See the Virtex-4 Data Sheet and the Virtex-5 Data Sheet for more information.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

101

UG181 June 27, 2008

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Xilinx UG181 manual DCM and Static Alignment Constraints, Phase Shift for DCM, Clock Delay in Iserdes

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

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