Source Behavior Before Synchronization

Chapter 4: Designing with the Core

Error Handling

This section describes how the Source core handles the receipt of non-compliant SPI-4.2 data and subsequent error handling in a number of common scenarios. This section also provides additional information on the Source core error status signals.

•To go into frame, the Source core must receive the number of complete status sequences defined by NumDip2Matches.

♦Each received status sequence must contain the correct number of entries (defined by SrcCalendar_Len* SrcCalendar_M) followed by the DIP-2 calculation and a frame word "11."

•When the core is out of sync, it will resychronize to the first "11-to-non-11" transition. Once it receives this transition, it will go in-frame once it receives the expected number of correct consecutive DIP-2 words.

•If there is a calendar mismatch with the receiving device, the core may not go into frame. If the mismatch causes DIP-2 errors, then SrcDIP2Err will be asserted.

•When the core is out of frame, every "11-to-non-11" transition is considered as a start of status sequence.

•The core checks if a "11" is received after an expected DIP-2 value is received. If a non ”11” frame word is received the SrcStatFrameErr signal will assert.

Source Behavior After Synchronization

•If the core receives an incorrect DIP-2 word, SrcDIP2Err flag will be asserted.

•If the core receives an incorrect frame word (not “11”), the SrcStatFrameErr flag will assert. This is another indication that the calendar is mismatched.

•After a specified number of consecutive DIP-2 Errors (defined by NumDip2Errors), the Source core will go out-of-frame.

•If the Source core receives four consecutive frame words ("11"), it will go out-of-frame.

•Once in frame, the core does not realign to the beginning of a status sequence. The assertion of DIP-2 errors would indicate a possible mismatch with the calendar of the receive device.

•A mismatch with the calendar of the receive device can be detected by polling that you have received a "11" as status on SrcStat.

EOP Abort Insertion

An EOP Abort will be inserted when a burst termination on a non-credit boundary without an EOP is followed by an SOP or an address change.

If a burst is paused on a non-credit boundary and then resumed with data (without an SOP) from the same channel, an EOP abort will not be inserted.

Source Out of Frame

Source Out of Frame (SrcOof) is asserted when the Source core is out-of-frame. The following cases can cause the Source core to go out-of-frame:

•Case 1: You reset the core by asserting Reset_n.

96	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Source Behavior Before Synchronization, Source Behavior After Synchronization

Models: UG181

Error Handling