Sink Core

R

•Initializing Status Calendar

After the core exits the reset mode, the sink and status calendars must be initialized or programmed. There are two ways to do this:

♦Initialize calendar with a default value: Using the CORE Generator GUI load an initialization file with the calendar contents. See Chapter 3, “Generating the Core” for more information.

♦Programming calendar after reset: Using the calendar control interface to program the calendar contents. See “Sink Calendar Initialization,” page 62 and “Source Calendar Initialization,” page 86 sections for more information.

After initializing the core, it can be enabled for operation.

Sink Core

Basic Operation

The Sink core receives data across the SPI-4.2 Lite interface and converts the 16-bit data into 32-bit or 64-bit data words that can be accessed on the user interface. It also transmits flow control information on the SPI-4.2 Lite interface by converting a 32-bit status bus to a 2-bit status word.

The following sections explain how the sink core interfaces operate. See “Sink Core

Interfaces,” page 19 for the signal list of each interface.

SPI-4.2 Interface

The SPI-4.2 data path combines 16-bit data words received on the SPI-4.2 Interface into 32- or 64-bit data words. This allows you interface to run at half (32-bit interface), or a quarter (64-bit interface) of the data rate. For example, for a 200 Mbps SPI-4.2 data rate and a 32-bit user interface, you can read data from the Sink core at 100 MHz. If a 64-bit user interface is used, data can be read from the Sink core at 50 MHz and maintain the same data rate.

After the data path combines the 16-bit data words received on the SPI-4.2 interface, the data words are written into an asynchronous FIFO. The received 16-bit control words are stored out of band in the FIFO, along with the corresponding data word. The received control words that are not idle (training words) can contain the information listed below:

•Start or continuation of the following packet

•Link address of the following packet

•End of the preceding packet

•Number of valid bytes in the last word of the preceding packet

•Error conditions in the preceding packet

For details about the assignment of each bit in the control word, as defined by the OIF SPI-

4.2specification, see Appendix A, “SPI-4.2 Lite Control Word.”

Sink Data Path: Example 1

Figure 4-1is an example of data received on the SPI-4.2 Interface and read on the 64-bit user interface. In this example, the first received control word (C1) is a payload resume (with no SOP) for channel 1, followed by two 16-bit words (channel 1, packet A and packet B). The second control word (C2) is an EOP for channel 1 and a payload resume for channel 2 (with no SOP), followed by two 16-bit words. The third control word (C3) is an EOP for

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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

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In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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