Xilinx Tool Flow, Example Design Script, NGDBuild

Chapter 7: Simulating and Implementing the Core

2.Add the necessary user source files to the project file.

3.Select target device and speed grade.

4.Synthesize the user application.

Xilinx Tool Flow

This section provides an overview of the Xilinx tool flow and discusses how to implement the SPI-4.2 Lite core and the user design with the Xilinx implementation tools. Detailed information about Xilinx tools can be found in the Xilinx Development System Reference Guide.

Before executing the Xilinx tool flow, a user design netlist must be generated where the SPI-4.2 Lite core is instantiated and all required constraints must be set in the user constraints file (ucf). See Chapter 5, “Constraining the Core,” for information about constraining the user design.

Example Design Script

An implementation script is provided with the example design to execute all the commands described below. This script can be used as an example of how to run the Xilinx tools with the SPI-4.2 Lite core. For details about the example design, see the SPI-4.2 Lite Getting Started Guide.

NGDBuild

Run ngdbuild to translate and merge the various source files of a design into a single NGD design database.

An example of the ngdbuild command is provided below:

ngdbuild <component_name>_top

The output of ngdbuild will be component_name_top.ngd.

Mapping the Design

To map the logic gates of the user’s design (previously written to an NGD file by ngdbuild) into the CLBs and IOBs of the physical device, the map command must be executed. The map command writes out this physical design to an NCD file. An example of the map command is provided below:

map -o mapped.ncd component_name_top.ngd

The map command outputs a mapped.ncd and mapped.pcf.

Place and Route

To place and route the user’s design logic components (mapped physical logic cells) contained within a NCD file based on the layout and timing requirements specified within the physical constraints file (PCF), the par command must be executed. An example of the par command is provided below:

par mapped.ncd routed.ncd

The par command outputs routed.ncd file that contains the placed and routed design.

128	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Xilinx Tool Flow, Example Design Script, NGDBuild, Mapping the Design

Models: UG181