Sink Core, Source Core, Core Architecture

Chapter 2: Core Architecture

data access and facilitates integration within a system. Dedicated signals are used to configure the Sink and Source cores in circuit and monitor a suite of status registers.

SPI-4.2	Virtex-4 or Spartan-3 Device		User
Interface			User
Interface			Interface
			Interface
	SPI-4.2 Lite Sink Core
Rx Data Path
	SPI-4.2	User
	Sink	Sink
Rx Status Path	Interface	Interface
SPI-4.2 Lite
PHY Layer Device			User’s Logic
(Xilinx FPGA	SPI-4.2 Lite Source Core		(Link Layer
or	SPI-4.2 Lite Source Core		Processor)
or			Processor)
ASSP)
Tx Data Path
	SPI-4.2	User
	Source	Source
Tx Status Path	Interface	Interface

Figure 2-1:SPI-4.2 Lite Core in a Typical Link Layer Application

Sink Core

The Sink core receives data from the SPI-4.2 interface. It takes the 16-bit interface and maps it to a 32-bit or 64-bit interface enabling the internal logic to run at a half (for 32-bit) or an quarter (for 64-bit) of the line rate. The user data and the corresponding control signals are accessed with a standard FIFO interface. The FIFO read and write operations are performed in independent clock domains.

The Sink core implements the following features:

•Supports 32-bit or 64-bit user data width

•Dedicated output signal indicating loss of valid RDClk

•Provides a FIFO reset signal for clearing contents of the data pipe during operation

•Provides support for forcing the insertion of DIP-2 errors for system testing

•Regional clocking option (for Virtex-4 and Virtex-5 devices only, saves global clocking resources)

•Provides both embedded and user clocking options

For more information on core features, see Chapter 4, “Designing with the Core.”

Source Core

The Source core transmits data on the SPI-4.2 interface. Payload data written into the core as 32-bit or 64-bit words (two or four 16-bit SPI-4.2 Lite words, respectively) are mapped onto the 16-bit SPI-4.2 interface. While packet data written into the core may not be 32-bit or 64-bit aligned, the core optimally maps the data to 16-bit words such that no filler idle cycles are inserted. The data along with the control signals are written into the core via a

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SPI-4.2 Lite v4.3 User Guide

UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Sink Core, Source Core, Core Architecture

Models: UG181