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Xilinx UG181 manual Sink Core, Source Core, Core Architecture

Models: UG181

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Chapter 2: Core Architecture

data access and facilitates integration within a system. Dedicated signals are used to configure the Sink and Source cores in circuit and monitor a suite of status registers.

	SPI-4.2	Virtex-4 or Spartan-3 Device		User
	Interface			User
	Interface			Interface
				Interface
		SPI-4.2 Lite Sink Core
	Rx Data Path
		SPI-4.2	User
		Sink	Sink
	Rx Status Path	Interface	Interface
	SPI-4.2 Lite
	PHY Layer Device			User’s Logic
	(Xilinx FPGA	SPI-4.2 Lite Source Core		(Link Layer
	or	SPI-4.2 Lite Source Core		Processor)
	or			Processor)
	ASSP)
	Tx Data Path
		SPI-4.2	User
		Source	Source
	Tx Status Path	Interface	Interface

Figure 2-1:SPI-4.2 Lite Core in a Typical Link Layer Application

Sink Core

The Sink core receives data from the SPI-4.2 interface. It takes the 16-bit interface and maps it to a 32-bit or 64-bit interface enabling the internal logic to run at a half (for 32-bit) or an quarter (for 64-bit) of the line rate. The user data and the corresponding control signals are accessed with a standard FIFO interface. The FIFO read and write operations are performed in independent clock domains.

The Sink core implements the following features:

•Supports 32-bit or 64-bit user data width

•Dedicated output signal indicating loss of valid RDClk

•Provides a FIFO reset signal for clearing contents of the data pipe during operation

•Provides support for forcing the insertion of DIP-2 errors for system testing

•Regional clocking option (for Virtex-4 and Virtex-5 devices only, saves global clocking resources)

•Provides both embedded and user clocking options

For more information on core features, see Chapter 4, “Designing with the Core.”

Source Core

The Source core transmits data on the SPI-4.2 interface. Payload data written into the core as 32-bit or 64-bit words (two or four 16-bit SPI-4.2 Lite words, respectively) are mapped onto the 16-bit SPI-4.2 interface. While packet data written into the core may not be 32-bit or 64-bit aligned, the core optimally maps the data to 16-bit words such that no filler idle cycles are inserted. The data along with the control signals are written into the core via a

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SPI-4.2 Lite v4.3 User Guide

UG181 June 27, 2008

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Xilinx UG181 manual Sink Core, Source Core, Core Architecture

Contents

LogiCORE IP SPI-4.2 Lite UG181 June 27SPI-4.2 Lite v4.3 User Guide UG181 June 27 Date Version RevisionTable of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide Schedule of Figures 1SPI-4.2 Lite Core in a Typical Link Layer Application30Addressable Status Fifo Interface 4-Channel Configuration Schedule of Tables Generating the Core Designing with the CoreAppendix a SPI-4.2 Lite Control Word Contents About This GuideConventions TypographicalOnline Document ConventionsPreface About This Guide Recommended Design Experience IntroductionAbout the Core Additional Core ResourcesSPI-4.2 Lite Core Technical SupportFeedback DocumentCore Architecture System OverviewSink Core Source CoreCore Architecture Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram Sink SPI-4.2 Interface RCtlNSink User Interface Sink Control and Status Interface3Sink Fifo Signals Name Sink Fifo InterfaceCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate Sink Clocking Interface RDClk0 General PurposeSource Core Interfaces RDClk0USER This clockSource SPI-4.2 Interface Source Core InterfacesSource User Interface DomainSource Control and Status Interface 16 bytes with no EOP Source Fifo Interface Name Direction Clock Description Domain14 Source Status Fifo Signals Source Static Configuration Interface Source Status AddressSource Almost Full Threshold Assert Source Clocking Interface Source Calendar Period The SrcCalendarMSysClk0 General Purpose Domain Core Architecture Generating the Core Core Generator Graphical User InterfaceComponent Name Main ScreenSink Status Options Screen Core OptionsCalendar Flow ControlStatus Interface Sink Other Options Screen SynchronizationFifo Threshold Clocking Clock ModeSource Status Options Screen Clock DistributionSource Other Options Screen BurstingSysClk Distribution Burst ModeBurst Size in Credits TSClk DistributionCalendar COE File Format General Design Guidelines Understand Signal PipeliningDesigning with the Core Know the Degree of DifficultyKeep it Registered Recognize Timing Critical SignalsInitializing the SPI-4.2 Lite Core Use Supported Design FlowsSPI-4.2 Interface Sink CoreBasic Operation Sink Data Path Example1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP RCtl Sink FifoSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Interface Signals Sink Fifo Almost EmptySink Fifo Empty Sink Almost FullSink Status and Flow Control Signals Sink OverflowSink Calendar Initialization Initializing the Calendar In-CircuitSink Flow Control 7Sink Calendar Initialization8Typical Flow Control Implementation for 4-Channel System Sink Status Fifo Interface Example 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3Sink Status Fifo Status Interface Example Fifo Almost Full Mode Sink Static Configuration SignalsInsertion of DIP2 Errors FifoAFMode and Sink Almost Full12FIFO Almost Full Mode Static Alignment Fifo Almost Full Mode 10 orSink Data Capture Implementation DCM Alignment Implementation ConsiderationsSynchronization and Start-up Reset HuntSync Wait Sync Train Error HandlingSync Data In-Frame and Out-of-Frame BehaviorEOP Abort Handling Sink Fifo Burst ErrorSink SPI-4.2 Bus Error and Sink Bus Error Status70 Loss of RDClkSink DIP-4 Error Handling Sequential Payload Control WordsSequential End-of-Burst Control Words 18Example of Error Flag SnkFFDIP4Err Source Core Reserved Control WordsSource Data Path Example Source Core22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Inserting DIP4 Errors Source Control and Status SignalsTransmitting Idle Cycles Source Fifo Interface Signals Source Fifo Almost FullSource Fifo Overflow 24Source Fifo Almost-full ConditionSource Status and Flow Control Signals Insertion of DIP-4 ErrorsWriting to the Source Fifo Source Calendar Initialization 27Typical User Design ExampleSource Flow Control Addressable Status Interface 28Source Calendar InitializationAddressable Status Fifo Interface Example 29Addressable Status Fifo Interface30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Static Configuration Signals Source Burst ModeSource Burst Mode Example 35Example Of Source Burst Mode =Reset EOP Abort Insertion Source Behavior Before SynchronizationSource Behavior After Synchronization Source Out of FrameSource Status Frame Word Handling Source DIP-2 Error HandlingSource Pattern Error Handling Incorrect Burst TerminationDesigning with the Core Sink Core Required Constraints Constraining the CoreOverview Timing ConstraintsTimespecs for Clocks Maxdelay for ResetTime Names for Clocks Constraining the CoreDCM and Static Alignment Constraints Phase Shift for DCMClock Delay in Iserdes Sink Core Required ConstraintsPlacement Constraints PlacementStandards Constraints IDelayCtrlSink Core Optional Constraints IOB Register PackingTiming Ignore Constraints Source Core Required ConstraintsArea Group Constraints Timenames for ClocksSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsUser Constraints Constraints MigrationNew Target Region or Device Package Sink Core Modifying the UCF FileTarget Device Source CoreInst TSClk LOC = Bank3 Special Design Considerations Sink Clocking OptionsEmbedded Clocking User Clocking Special Design ConsiderationsGlobal Clocking Sink Clocking Options2Sink Core User Clocking Resources Clocking Option Regional Clocking 3Sink User Clocking Global ClockingSource Clocking Options Source Clocking OptionsMaster Clocking 5Source Clocking Master and Slave ImplementationIOB 8Source Clocking Regional Clocking for SysClk Slave Clocking 3SysClk Clocking Resources Clocking OptionTSClk Clocking Resources Clocking Option Multiple Core Implementations Instantiating Multiple CoresGenerating the Cores Creating Top-Level UCF FileMultiple Core Implementations Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Generating a Simulation Model Simulating and Implementing the CoreFunctional Simulation Generating a Simulation Model with Initialized CalendarTiming Simulation Simulating and Implementing the CoreSynplify SynthesisSynthesis of Example Design SynthesisNGDBuild Xilinx Tool FlowExample Design Script Mapping the DesignStatic Timing Analysis Generating a BitstreamXilinx Tool Flow 130 SPI-4.2 Lite Control Word EopsDIP-4 SPI-4.2 Lite Calendar Programming ExampleAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification