Error Handling, Sync Data, Sync Train | Xilinx UG181 specification

Chapter 4: Designing with the Core

Sync Data

In the Sync Data state, normal core operation is enabled.

In this state, the Sink core continuously checks DIP-4 parity, stores data received on RDat[15:0] into the Sink FIFO, and sends FIFO Channel status on RStat. The core is In Frame in this state.

Sync Train

The Sink core enters the Sync Train state when a training pattern is detected on RDat[15:0]. The Sink core stops storing data to the Sink FIFO while in this state. The core remains in this state while training is received on RDat.

In this state, the Sink core continuously checks DIP-4 parity, and sends FIFO Channel status on RStat. The core is In Frame in this state.

In-Frame and Out-of-Frame Behavior

There are a number of conditions that must be met before the Sink core deasserts SnkOof and starts accepting data. Data will be written to the FIFO when the following conditions are met:

•Reset_n is deasserted

•SnkFifoReset_n is deasserted

•SnkEn is asserted

•SnkOof is deasserted (NumTrainSequences consecutive training patterns received)

•First valid SOP-to-data transition detected (after SnkOof or SnkFifoReset_n deasserted)

Three conditions will cause the Sink core to lose synchronization and assert SnkOof. The core stops writing data to the FIFO when any of these conditions occur.

•SnkEn is deasserted

•SnkAlmostFull_n asserted and SnkFifoAFMode = Send Framing Patterns ("00")

•NumDip4Errors consecutive DIP4 errors are detected

Error Handling

This section describes how the Sink core handles receiving non-compliant SPI-4.2 data and subsequent error handling in a number of common scenarios. This section also provides information on the Sink core error status signals.

Short Packet Support (less than 16-byte packet support)

Though the SPI-4.2 specification requires that successive start-of-packets must occur not less than eight cycles apart, there is no restriction on payload control words—which are not SOPs. The Sink core automatically handles any size packets, including multiple SOP that are less than eight cycles apart. If SOPs are less than eight cycles apart, the data will be passed through the core correctly, but the status output SnkBusErr will be flagged to indicate a protocol violation.

72	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.

Xilinx UG181 manual Error Handling, Sync Data, Sync Train, In-Frame and Out-of-Frame Behavior

Models: UG181